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mainboard/volteer: Configure UsbTcPortEn value 

The default value is not sufficient to correctly configure the Type-C
ports as it has all ports disabled by default. On Volteer ports 0
and 1 are enabled so setting this value to 0x3 and correctly
keeping the IomPortPadCfg values at 0 for ports that have a
retimer and ports that are not configured. These values were set
to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn
value being incorrect.

BUG=b:159151238
BRANCH=firmware-volteer-13672.B
TEST=Built image for Voxel and verified that s0ix cycles complete
     without any issues

Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Brandon Breitenstein 2020-12-21 14:57:50 -08:00 committed by Tim Wawrzynczak
parent bf50c31184
commit 40b5358c2a
1 changed files with 1 additions and 8 deletions
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9
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -221,16 +221,9 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkSndwEnable[1]" = "0"
# TCSS USB3
register "UsbTcPortEn" = "0x3"
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
register "IomTypeCPortPadCfg[0]" = "0x09000000"
register "IomTypeCPortPadCfg[1]" = "0x09000000"
register "IomTypeCPortPadCfg[2]" = "0x09000000"
register "IomTypeCPortPadCfg[3]" = "0x09000000"
register "IomTypeCPortPadCfg[4]" = "0x09000000"
register "IomTypeCPortPadCfg[5]" = "0x09000000"
register "IomTypeCPortPadCfg[6]" = "0x09000000"
register "IomTypeCPortPadCfg[7]" = "0x09000000"
# DP port
register "DdiPortAConfig" = "1" # eDP