mb/facebook/monolith/gpio.h: Update GPIO configuration
Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Wim Vervoorn
Patrick Georgi
parent
8d9262a7e7
commit
40bb6c340f
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@ -21,154 +21,141 @@
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
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#define EC_SCI_GPI GPE0_DW2_16
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#define EC_SMI_GPI GPP_E15
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
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/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
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/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
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/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
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/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
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///* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
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/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
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/* PCH_RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
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/* LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
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/* LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
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/* LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
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/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* PCH_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* PIRQA# */ PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* PM_CLKRUN_N */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
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/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
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/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */
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/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
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/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_A12),
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/* PCH_SYSWARN */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
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/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
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/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
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/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
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/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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/* V0.85A_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* V0.85A_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* GP_VRALERTB */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B4),
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/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5),
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/* CLK_REQ_SLOT1 */ PAD_CFG_NC(GPP_B6),
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/* CLK_REQ_SLOT2 */ PAD_CFG_NC(GPP_B7),
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/* CLK_REQ_SLOT3 */ PAD_CFG_NC(GPP_B8),
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/* CLK_REQ_SLOT4 */ PAD_CFG_NC(GPP_B9),
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/* CLK_REQ_SLOT5 */ PAD_CFG_NC(GPP_B10),
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/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* GSPI0_CS# */ /* GPP_B15 */
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/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
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/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
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/* NC */ PAD_CFG_NC(GPP_A18),
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/* NC */ PAD_CFG_NC(GPP_A19),
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/* NC */ PAD_CFG_NC(GPP_A20),
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/* NC */ PAD_CFG_NC(GPP_A21),
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/* NC */ PAD_CFG_NC(GPP_A22),
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/* NC */ PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
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/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_B3),
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/* NC */ PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ0 */ PAD_CFG_NC(GPP_B5),
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/* SRCCLKREQ1 */ PAD_CFG_NC(GPP_B6),
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/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7),
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/* SRCCLKREQ3 */ PAD_CFG_NC(GPP_B8),
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/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9),
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/* SRCCLKREQ5 */ PAD_CFG_NC(GPP_B10),
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/* EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PCH_PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_B15),
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/* NC */ PAD_CFG_NC(GPP_B16),
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/* NC */ PAD_CFG_NC(GPP_B17),
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/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
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/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
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/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
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/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
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///* CB_OVT# */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
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/* SML1ALERT# */ PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST),
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/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_B19),
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/* NC */ PAD_CFG_NC(GPP_B20),
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/* NC */ PAD_CFG_NC(GPP_B21),
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/* BIOS_SEL */ PAD_CFG_NC(GPP_B22),
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/* CB_OVT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP),
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/* SMB_SCL */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMB_SDA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP),
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/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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///* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST),
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/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
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/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* UART1_RXD */ PAD_CFG_NC(GPP_C12),
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/* UART1_TXD */ PAD_CFG_NC(GPP_C13),
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/* UART1_RTS */ PAD_CFG_NC(GPP_C14),
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/* UART1_CTS */ PAD_CFG_NC(GPP_C15),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
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/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),
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/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
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/* UART2_RXD */ PAD_CFG_NC(GPP_C20),
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/* UART2_TXD */ PAD_CFG_NC(GPP_C21),
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///* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
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///* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
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/* EC_SCI# not used */ PAD_CFG_NC(GPP_C22),
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/* EC_SMI# not used */ PAD_CFG_NC(GPP_C23),
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/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
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/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
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/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* GPP_D9 */ PAD_CFG_NC(GPP_D9),
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/* GPP_D10 */ PAD_CFG_NC(GPP_D10),
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/* GPP_D11 */ PAD_CFG_NC(GPP_D11),
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/* GPP_D12 */ PAD_CFG_NC(GPP_D12),
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/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
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/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
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/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),
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/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),
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/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17),
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/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18),
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/* DMIC_CLK_0 */ PAD_CFG_NC(GPP_D19),
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/* DMIC_DATA_0 */ PAD_CFG_NC(GPP_D20),
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/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
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/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
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///* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
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/* GPP_E0 */ PAD_CFG_NC(GPP_E0),
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/* GPP_E1 */ PAD_CFG_NC(GPP_E1),
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/* GPP_E2 */ PAD_CFG_NC(GPP_E2),
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/* GPP_E3 */ PAD_CFG_NC(GPP_E3),
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/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
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/* GPP_E7 */ PAD_CFG_NC(GPP_E7),
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/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST),
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/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* DDI3_HPD */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
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/* DDI4_HPD */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* SML0_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* SML0_ALERT */ PAD_CFG_NC(GPP_C5),
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/* GPP_C6 - RESERVED */
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/* GPP_C7 - RESERVED */
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/* CPU_UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* CPU_UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* CPU_UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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/* CPU_UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_C12),
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/* NC */ PAD_CFG_NC(GPP_C13),
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/* NC */ PAD_CFG_NC(GPP_C14),
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/* NC */ PAD_CFG_NC(GPP_C15),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* NC */ PAD_CFG_NC(GPP_C18),
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/* NC */ PAD_CFG_NC(GPP_C19),
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/* NC */ PAD_CFG_NC(GPP_C20),
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/* NC */ PAD_CFG_NC(GPP_C21),
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/* EC_SCI# NOT USED */ PAD_CFG_NC(GPP_C22),
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/* EC_SMI# NOT USED */ PAD_CFG_NC(GPP_C23),
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/* TOUCH_SPI1_CS */ PAD_CFG_NC(GPP_D0),
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/* TPM_PIRQ_N NOT USED */ PAD_CFG_NC(GPP_D1),
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/* NC */ PAD_CFG_NC(GPP_D2),
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/* NC */ PAD_CFG_NC(GPP_D3),
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/* NC */ PAD_CFG_NC(GPP_D4),
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/* NC */ PAD_CFG_NC(GPP_D5),
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/* NC */ PAD_CFG_NC(GPP_D6),
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/* NC */ PAD_CFG_NC(GPP_D7),
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/* NC */ PAD_CFG_NC(GPP_D8),
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/* NC */ PAD_CFG_NC(GPP_D9),
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/* NC */ PAD_CFG_NC(GPP_D11),
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/* NC */ PAD_CFG_NC(GPP_D12),
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/* NC */ PAD_CFG_NC(GPP_D13),
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/* NC */ PAD_CFG_NC(GPP_D14),
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/* NC */ PAD_CFG_NC(GPP_D15),
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/* NC */ PAD_CFG_NC(GPP_D16),
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/* NC */ PAD_CFG_NC(GPP_D17),
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/* NC */ PAD_CFG_NC(GPP_D18),
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/* NC */ PAD_CFG_NC(GPP_D19),
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/* NC */ PAD_CFG_NC(GPP_D20),
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/* LID# NOT USED */ PAD_CFG_NC(GPP_D21),
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/* NC */ PAD_CFG_NC(GPP_D22),
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/* NC */ PAD_CFG_NC(GPP_D23),
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/* NC */ PAD_CFG_NC(GPP_E0),
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/* NC */ PAD_CFG_NC(GPP_E1),
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/* NC */ PAD_CFG_NC(GPP_E2),
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/* NC */ PAD_CFG_NC(GPP_E3),
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/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E4),
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/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E5),
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/* DEVSLP1 TP */ PAD_CFG_NC(GPP_E6),
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/* NC */ PAD_CFG_NC(GPP_E7),
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/* SATA_LED_N */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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/* USB2_OC0_1 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2_OC2_3 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* USB2_OC4_5 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB2_OC6_7 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* DDPB_HPD0_C */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDPC_HPD1_C */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* DDPD_HPD2_C NC */ PAD_CFG_NC(GPP_E15),
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/* DDPE_HPD3_C NC */ PAD_CFG_NC(GPP_E16),
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/* EDP_HPD_C */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
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/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
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/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
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/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1),
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/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
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/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
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/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
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/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
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/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
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/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
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/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
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/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
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/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),
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||||
/* I2C4_SDA */ PAD_CFG_NC(GPP_F9),
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/* ISH_I2C2_SDA */ PAD_CFG_NC(GPP_F10),
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/* ISH_I2C2_SCL */ PAD_CFG_NC(GPP_F11),
|
||||
/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
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/* DDI2_DDC_SCL_L */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
|
||||
/* DDPD_CTRLCLK NC */ PAD_CFG_NC(GPP_E22),
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/* DDPD_CTRLDAT NC */ PAD_CFG_NC(GPP_E23),
|
||||
/* NC */ PAD_CFG_NC(GPP_F0),
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||||
/* NC */ PAD_CFG_NC(GPP_F1),
|
||||
/* NC */ PAD_CFG_NC(GPP_F2),
|
||||
/* NC */ PAD_CFG_NC(GPP_F3),
|
||||
/* NC */ PAD_CFG_NC(GPP_F4),
|
||||
/* NC */ PAD_CFG_NC(GPP_F5),
|
||||
/* NC */ PAD_CFG_NC(GPP_F6),
|
||||
/* NC */ PAD_CFG_NC(GPP_F7),
|
||||
/* NC */ PAD_CFG_NC(GPP_F8),
|
||||
/* NC */ PAD_CFG_NC(GPP_F9),
|
||||
/* NC */ PAD_CFG_NC(GPP_F10),
|
||||
/* NC */ PAD_CFG_NC(GPP_F11),
|
||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
|
|
@ -178,29 +165,29 @@ static const struct pad_config gpio_table[] = {
|
|||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* EMMC_STROBE */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* GPP_F23 */ PAD_CFG_NC(GPP_F23),
|
||||
/* GPP_F23 */ PAD_CFG_NC(GPP_F23),
|
||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_D0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_D1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_D2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_D3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
|
||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
|
||||
/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7 */ PAD_CFG_NC(GPD7),
|
||||
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
/* KBC_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* PCH_LAN_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* KBC_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* PM_SLP_M_N */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* BIOS_RECOVERY NOT USED */ PAD_CFG_NC(GPD7),
|
||||
/* CPU_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* PCH_LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue