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soc/amd/picasso: Update machine check support 

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33769
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2019-06-20 14:18:05 -06:00 committed by Martin Roth
parent c17cc63e48
commit 40bc485745
1 changed files with 1 additions and 8 deletions
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9
src/soc/amd/picasso/mca.c
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@ -97,11 +97,6 @@ static void fill_generic_section(cper_proc_generic_error_section_t *sec,
* which is the best method to report MSR context. As a result, add two
* structures: A "processor generic error" that is parsed, and an IA32/X64 one
* to capture complete information.
*
* Future work may attempt to interpret the specific Family 15h error symptoms
* found in the MCA registers. This data could enhance the reporting of the
* Processor Generic section and the failing error/check added to the
* IA32/X64 section.
*/
static void build_bert_mca_error(struct mca_bank *mci)
{
@ -161,6 +156,7 @@ static const char *const mca_bank_name[] = {
"Floating point unit"
};
/* Check the Legacy Machine Check Architecture registers */
void check_mca(void)
{
int i;
@ -173,9 +169,6 @@ void check_mca(void)
if (is_warm_reset()) {
for (i = 0 ; i < num_banks ; i++) {
if (i == 3) /* Reserved in Family 15h */
continue;
mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4));
if (mci.sts.hi || mci.sts.lo) {
int core = cpuid_ebx(1) >> 24;