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mb/google/brask/variants/moli: add delay time to rtd3-cold 

This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence,
the reason is that the rise and fall times of each signal
may differ by board, and so those board-specific delays
must be taken into account when power sequencing.

We checked power on sequence requires enable pin prior to reset pin,
so added delay to meet the sequence.
Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.

BUG=b:228907551
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Raihow Shi 2022-04-11 17:22:51 +08:00 committed by Felix Held
parent b83dd7ea63
commit 40c47b24a4
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/brya/variants/moli/overridetree.cb
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@ -100,6 +100,8 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "srcclk_pin" = "1" register "srcclk_pin" = "1"
register "reset_delay_ms" = "50"
register "enable_delay_ms" = "20"
device generic 0 alias emmc_rtd3 on end device generic 0 alias emmc_rtd3 on end
end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1 end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
register "pch_pcie_rp[PCH_RP(12)]" = "{ register "pch_pcie_rp[PCH_RP(12)]" = "{