mb/google/reef: Add method to set GPIOs in romstage

Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2022-12-20 16:20:18 -06:00 committed by Martin L Roth
parent 0d54a65819
commit 40c8cc9cde
4 changed files with 16 additions and 0 deletions

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@ -3,11 +3,18 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <soc/meminit.h> #include <soc/meminit.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)
{ {
const struct pad_config *pads;
size_t pads_num;
meminit_lpddr4_by_sku(&memupd->FspmConfig, meminit_lpddr4_by_sku(&memupd->FspmConfig,
variant_lpddr4_config(), variant_memory_sku()); variant_lpddr4_config(), variant_memory_sku());
pads = variant_romstage_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
} }
void mainboard_save_dimm_info(void) void mainboard_save_dimm_info(void)

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@ -1,5 +1,6 @@
bootblock-y += gpio.c bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c romstage-y += memory.c
ramstage-y += gpio.c ramstage-y += gpio.c

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@ -392,6 +392,13 @@ variant_sleep_gpio_table(u8 slp_typ, size_t *num)
return sleep_gpio_table; return sleep_gpio_table;
} }
/* Weak implementation of romstage gpio */
const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),

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@ -16,6 +16,7 @@ const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num);
const struct pad_config *variant_sku_gpio_table(size_t *num); const struct pad_config *variant_sku_gpio_table(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);
/* Baseboard default swizzle. Can be reused if swizzle is same. */ /* Baseboard default swizzle. Can be reused if swizzle is same. */
extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;