mb/google/guybrush: Reorganize bootblock_mainboard_early_init()
This now skips all of the pieces done by PSP_verstage. BUG=None TEST=Boot Guybrush with & without PSP_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -31,21 +31,6 @@ void bootblock_mainboard_early_init(void)
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size_t base_num_gpios, override_num_gpios;
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const struct soc_amd_gpio *base_gpios, *override_gpios;
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if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
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base_gpios = variant_early_gpio_table(&base_num_gpios);
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override_gpios = variant_early_override_gpio_table(&override_num_gpios);
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gpio_configure_pads_with_override(base_gpios, base_num_gpios,
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override_gpios, override_num_gpios);
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/* Set a timer to make sure there's enough delay for
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* the Fibocom 350 PCIe init
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*/
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stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
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}
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printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
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dword = pci_read_config32(SOC_LPC_DEV, 0x78);
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dword &= 0xFFFFF9F3;
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dword |= 0x200;
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@ -53,6 +38,21 @@ void bootblock_mainboard_early_init(void)
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pci_write_config32(SOC_LPC_DEV, 0x44, 0);
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pci_write_config32(SOC_LPC_DEV, 0x48, 0);
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if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
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return;
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base_gpios = variant_early_gpio_table(&base_num_gpios);
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override_gpios = variant_early_override_gpio_table(&override_num_gpios);
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gpio_configure_pads_with_override(base_gpios, base_num_gpios,
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override_gpios, override_num_gpios);
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/* Set a timer to make sure there's enough delay for
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* the Fibocom 350 PCIe init
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*/
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stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
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printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
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dword = pm_read32(0x90);
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dword |= 1 << 16;
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pm_write32(0x90, dword);
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