Add AMD rs690 VID DID reporting and some minor cleanups.
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joe Bao
Marc Jones
parent
164463c551
commit
40d46ba383
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@ -21,9 +21,9 @@
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#define RS690_CHIP_H
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/* Member variables are defined in Config.lb. */
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struct southbridge_amd_rs690_config
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struct southbridge_amd_rs690_config
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{
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unsigned long vga_rom_address; /* The location that the VGA rom has been appened. */
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u32 vga_rom_address; /* The location that the VGA rom has been appened. */
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u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
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u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
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u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
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@ -29,25 +29,6 @@
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#include <cpu/amd/mtrr.h>
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#include "rs690.h"
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static device_t find_nb_dev(device_t dev, u32 devfn)
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{
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device_t nb_dev;
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nb_dev = dev_find_slot(dev->bus->secondary, devfn);
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if (!nb_dev)
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return nb_dev;
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if ((nb_dev->vendor != PCI_VENDOR_ID_ATI)
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|| (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) {
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u32 id;
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id = pci_read_config32(nb_dev, PCI_VENDOR_ID);
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if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) {
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nb_dev = 0;
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}
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}
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return nb_dev;
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}
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/*****************************************
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* Compliant with CIM_33's ATINB_MiscClockCtrl
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@ -65,7 +46,7 @@ void static rs690_config_misc_clk(device_t nb_dev)
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word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
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word &= 0xf00;
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pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
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pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
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word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
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word &= ~((1 << 12) | (1 << 13) | (1 << 14));
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@ -123,6 +104,12 @@ void static rs690_config_misc_clk(device_t nb_dev)
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set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
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}
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u32 get_vid_did(device_t dev)
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{
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return pci_read_config32(dev, 0);
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}
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/***********************************************
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* 0:00.0 NBCFG :
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* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
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@ -140,39 +127,25 @@ void static rs690_config_misc_clk(device_t nb_dev)
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void rs690_enable(device_t dev)
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{
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device_t nb_dev = 0, sb_dev = 0;
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int index = -1;
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u32 i;
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u32 devfn;
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u32 deviceid, vendorid;
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int dev_ind;
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vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
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deviceid = (vendorid >> 16) & 0xffff;
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vendorid &= 0xffff;
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printk_info("rs690_enable VID=0x%x, DID=0x%x\n", vendorid, deviceid);
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printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev));
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/**********************************************************
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* Work for bus0, internal GFX located on bus1 and will return after find_nb_dev.
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**********************************************************/
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i = (dev->path.u.pci.devfn) & ~7;
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for (devfn = 0; devfn <= i; devfn += (1 << 3)) {
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nb_dev = find_nb_dev(dev, devfn);
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if (nb_dev)
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break;
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}
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nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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printk_info("CAN NOT FIND RS690 DEVICE!\n");
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return; /* nb_dev is not dev */
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die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n");
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/* NOT REACHED */
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}
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/* sb_dev (dev 8) is a bridge that links to southbridge. */
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sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
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if (!sb_dev) {
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printk_info("rs690_enable CAN NOT FIND SB bridge, HALT!\n");
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for (;;) ;
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die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n");
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/* NOT REACHED */
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}
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printk_info("rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3);
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switch (dev->path.u.pci.devfn - devfn) {
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dev_ind = dev->path.u.pci.devfn >> 3;
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switch (dev_ind) {
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case 0: /* bus0, dev0, fun0; */
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printk_info("Bus-0, Dev-0, Fun-0.\n");
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enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
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@ -185,36 +158,34 @@ void rs690_enable(device_t dev)
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rs690_config_misc_clk(nb_dev);
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break;
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case 1 << 3: /* bus0, dev1 */
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case 1: /* bus0, dev1 */
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printk_info("Bus-0, Dev-1, Fun-0.\n");
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break;
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case 2 << 3: /* bus0, dev2,3, two GFX */
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case 3 << 3:
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case 2: /* bus0, dev2,3, two GFX */
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case 3:
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printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
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index = (dev->path.u.pci.devfn - devfn) >> 3;
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
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(dev->enabled ? 0 : 1) << index);
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
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(dev->enabled ? 0 : 1) << dev_ind);
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if (dev->enabled)
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rs690_gfx_init(nb_dev, dev, index);
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rs690_gfx_init(nb_dev, dev, dev_ind);
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break;
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case 4 << 3: /* bus0, dev4-7, four GPP */
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case 5 << 3:
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case 6 << 3:
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case 7 << 3:
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case 4: /* bus0, dev4-7, four GPP */
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case 5:
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case 6:
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case 7:
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printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
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dev->enabled);
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index = (dev->path.u.pci.devfn - devfn) >> 3;
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
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(dev->enabled ? 0 : 1) << index);
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
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(dev->enabled ? 0 : 1) << dev_ind);
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if (dev->enabled)
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rs690_gpp_sb_init(nb_dev, dev, index);
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rs690_gpp_sb_init(nb_dev, dev, dev_ind);
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break;
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case 8 << 3: /* bus0, dev8, SB */
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case 8: /* bus0, dev8, SB */
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printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
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set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
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(dev->enabled ? 1 : 0) << 6);
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if (dev->enabled)
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rs690_gpp_sb_init(nb_dev, dev, index);
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rs690_gpp_sb_init(nb_dev, dev, dev_ind);
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disable_pcie_bar3(nb_dev);
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break;
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default:
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@ -63,8 +63,8 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
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/*get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c);
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printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.u.pci.devfn);
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/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.u.pci.devfn);*/
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addr |= dev->bus->secondary << 20 | /* bus num */
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dev->path.u.pci.devfn << 12 | reg_pos;
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@ -18,7 +18,6 @@
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*/
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#define NBHTIU_INDEX 0xA8
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#define NBMISC_INDEX 0x60
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#define NBMC_INDEX 0xE8
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@ -185,7 +184,7 @@ static void rs690_htinit()
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* get k8's ht freq, in k8's function 0, offset 0x88
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* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
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* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
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* value to this reg, and that value takes effect on the next warm reset or
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* value to this reg, and that value takes effect on the next warm reset or
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* LDTSTOP_L disconnect sequence.
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* 0000b = 200Mhz
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* 0010b = 400Mhz
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@ -300,7 +299,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev)
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/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
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* force this BAR as mem type in rs690_gfx.c */
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set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
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}
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/*****************************************
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@ -72,7 +72,7 @@ static void rs690_gfx_read_resources(device_t dev)
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static void internal_gfx_pci_dev_init(struct device *dev)
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{
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unsigned short deviceid, vendorid;
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u16 deviceid, vendorid;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)dev->chip_info;
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deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
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@ -109,11 +109,6 @@ static void internal_gfx_pci_dev_init(struct device *dev)
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clkind_write(dev, 0x5C, 0x0);
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}
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static void rs690_gfx_set_resources(struct device *dev)
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{
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printk_info("rs690_gfx_set_resources.\n");
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pci_dev_set_resources(dev);
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}
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/*
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* Set registers in RS690 and CPU to enable the internal GFX.
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@ -137,7 +132,7 @@ static void rs690_internal_gfx_enable(device_t dev)
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/* set TOM */
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rs690_set_tom(nb_dev);
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/* LPC DMA Deadlock workaround? */
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k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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l_dword = pci_read_config32(k8_f0, 0x68);
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@ -206,9 +201,9 @@ static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations ht_ops = {
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static struct device_operations pcie_ops = {
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.read_resources = rs690_gfx_read_resources,
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.set_resources = rs690_gfx_set_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs690_gfx_init, */
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.scan_bus = 0,
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@ -216,8 +211,8 @@ static struct device_operations ht_ops = {
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.ops_pci = &lops_pci,
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};
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static struct pci_driver internal_gfx_driver __pci_driver = {
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.ops = &ht_ops,
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static struct pci_driver pcie_driver __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX,
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};
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@ -350,7 +345,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
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}
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/* For single port GFX configuration Only
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/* For single port GFX configuration Only
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* width:
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* 000 = x16
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* 001 = x1
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@ -492,7 +487,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
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set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
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printk_info("rs690_gfx_init step8.3.\n");
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/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
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/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
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* time out and go back to Detect Idle.*/
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set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
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printk_info("rs690_gfx_init step8.4.\n");
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@ -510,7 +505,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
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set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
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printk_info("rs690_gfx_init step8.8.\n");
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/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
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/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
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* SLOT_IMPLEMENTED@PCIE_CAP */
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reg16 = pci_read_config16(dev, 0x5a);
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reg16 |= 0x100;
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@ -563,7 +558,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
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/* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */
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/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
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/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
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* While details will be added later in the document, for now assue the single-port configuration. */
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/* skip */
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@ -61,7 +61,7 @@ static void pcie_init(struct device *dev)
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dword |= (1 << 30); /* Clear possible errors */
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pci_write_config32(dev, 0x04, dword);
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/*
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/*
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* 1 is APIC enable
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* 18 is enable nb to accept A4 interrupt request from SB.
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*/
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@ -116,37 +116,6 @@ static void pcie_init(struct device *dev)
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pci_write_config32(dev, 0x04, dword);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = 0,
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};
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static struct device_operations pcie_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pcie_init,
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.scan_bus = pci_scan_bridge,
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/*.enable = rs690_enable, */
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.ops_pci = &lops_pci,
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};
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static struct pci_driver pcie_driver __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE,
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};
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static struct pci_driver pcie_driver_dev7 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7,
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};
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static struct pci_driver pcie_driver_dev8 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
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};
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/**********************************************************************
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**********************************************************************/
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static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
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