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mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17

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Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2021-02-20 13:52:52 +05:30 committed by Patrick Georgi
parent cbcae2744a
commit 40f53f4b87
4 changed files with 10 additions and 3 deletions
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3
src/mainboard/intel/adlrvp/include/baseboard/variants.h
View file

@ -15,7 +15,8 @@ enum adl_boardid {
/* ADL-P DDR5 RVPs */
ADL_P_DDR5 = 0x12,
/* ADL-P LPDDR5 RVP */
ADL_P_LP5 = 0x13,
ADL_P_LP5_1 = 0x13,
ADL_P_LP5_2 = 0x17,
/* ADL-P DDR4 RVPs */
ADL_P_DDR4_1 = 0x14,
ADL_P_DDR4_2 = 0x3F,

3
src/mainboard/intel/adlrvp/memory.c
View file

@ -171,7 +171,8 @@ const struct mb_cfg *variant_memory_params(void)
return &ddr4_mem_config;
case ADL_P_DDR5:
return &ddr5_mem_config;
case ADL_P_LP5:
case ADL_P_LP5_1:
case ADL_P_LP5_2:
return &lp5_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);

3
src/mainboard/intel/adlrvp/romstage_fsp_params.c
View file

@ -57,7 +57,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
break;
case ADL_P_LP4_1:
case ADL_P_LP4_2:
case ADL_P_LP5:
case ADL_P_LP5_1:
case ADL_P_LP5_2:
memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
break;
default:

4
src/mainboard/intel/adlrvp/spd/Makefile.inc
View file

@ -4,3 +4,7 @@ SPD_SOURCES = adlrvp_lp4 # 0b000
SPD_SOURCES += empty # 0b001
SPD_SOURCES += empty # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += empty # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007