diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 7adaa30b18..2239f137c1 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -211,21 +211,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
 	return dram_base;
 }
 
-/*
- * SoC implementation
- *
- * SoC call to summarize all Intel Reserve MMIO size and report to SA
- */
-size_t soc_reserved_mmio_size(void)
-{
-	struct ebda_config cfg;
-
-	retrieve_ebda_object(&cfg);
-
-	/* Get Intel Reserved Memory Range Size */
-	return cfg.reserved_mem_size;
-}
-
 /* Fill up memory layout information */
 void fill_soc_memmap_ebda(struct ebda_config *cfg)
 {
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 133047c5b7..ae9213c395 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -106,8 +106,4 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt);
 /* SoC specific APIs to get UNCORE PRMRR base and mask values
  * returns 0, if able to get base and mask values; otherwise returns -1 */
 int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask);
-
-/* SoC call to summarize all Intel Reserve MMIO size and report to SA */
-size_t soc_reserved_mmio_size(void);
-
 #endif	/* SOC_INTEL_COMMON_BLOCK_SA_H */
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 0312cac94e..e03942fb30 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -46,11 +46,6 @@ __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base,
 	return -1;
 }
 
-__weak size_t soc_reserved_mmio_size(void)
-{
-	return 0;
-}
-
 __weak unsigned long sa_write_acpi_tables(struct device *dev,
 					  unsigned long current,
 					  struct acpi_rsdp *rsdp)
@@ -125,8 +120,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
  * These are the host memory ranges that should be added:
  * - 0 -> 0xa0000: cacheable
  * - 0xc0000 -> top_of_ram : cacheable
- * - top_of_ram -> TSEG - DPR: uncacheable
- * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved
+ * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved
  * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
  * - 4GiB -> TOUUD: cacheable
  *
@@ -155,18 +149,11 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
 static void sa_add_dram_resources(struct device *dev, int *resource_count)
 {
 	uintptr_t base_k, touud_k;
-	size_t dpr_size = 0, size_k;
-	size_t reserved_mmio_size;
+	size_t size_k;
 	uint64_t sa_map_values[MAX_MAP_ENTRIES];
 	uintptr_t top_of_ram;
 	int index = *resource_count;
 
-	if (CONFIG(SA_ENABLE_DPR))
-		dpr_size = sa_get_dpr_size();
-
-	/* Get SoC reserve memory size as per user selection */
-	reserved_mmio_size = soc_reserved_mmio_size();
-
 	top_of_ram = (uintptr_t)cbmem_top();
 
 	/* 0 - > 0xa0000 */
@@ -181,14 +168,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
 
 	sa_get_mem_map(dev, &sa_map_values[0]);
 
-	/* top_of_ram -> TSEG - DPR - Intel Reserve Memory Size*/
+	/* top_of_ram -> BGSM */
 	base_k = top_of_ram;
-	size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k
-			- reserved_mmio_size;
-	mmio_resource(dev, index++, base_k / KiB, size_k / KiB);
-
-	/* TSEG - DPR - Intel Reserve Memory Size -> BGSM */
-	base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size;
 	size_k = sa_map_values[SA_BGSM_REG] - base_k;
 	reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB);
 
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 20c4e6fb7d..122cb1a009 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -190,21 +190,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
 	return dram_base;
 }
 
-/*
- * SoC implementation
- *
- * SoC call to summarize all Intel Reserve MMIO size and report to SA
- */
-size_t soc_reserved_mmio_size(void)
-{
-	struct ebda_config cfg;
-
-	retrieve_ebda_object(&cfg);
-
-	/* Get Intel Reserved Memory Range Size */
-	return cfg.reserved_mem_size;
-}
-
 /* Fill up memory layout information */
 void fill_soc_memmap_ebda(struct ebda_config *cfg)
 {
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f2790efb35..780c73c298 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -212,21 +212,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
 	return dram_base;
 }
 
-/*
- * SoC implementation
- *
- * SoC call to summarize all Intel Reserve MMIO size and report to SA
- */
-size_t soc_reserved_mmio_size(void)
-{
-	struct ebda_config cfg;
-
-	retrieve_ebda_object(&cfg);
-
-	/* Get Intel Reserved Memory Range Size */
-	return cfg.reserved_mem_size;
-}
-
 /* Fill up memory layout information */
 void fill_soc_memmap_ebda(struct ebda_config *cfg)
 {