Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3x[84:80], ACPI Power State Control Registers, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -258,7 +258,6 @@ static void config_power_ctrl_misc_reg(device_t dev) {
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}
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}
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}
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}
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static void config_nb_syn_ptr_adj(device_t dev) {
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static void config_nb_syn_ptr_adj(device_t dev) {
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/* Note the following settings are additional from the ported
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/* Note the following settings are additional from the ported
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* function setFidVidRegs()
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* function setFidVidRegs()
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@ -269,6 +268,14 @@ static void config_nb_syn_ptr_adj(device_t dev) {
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}
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}
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static void config_acpi_pwr_state_ctrl_regs(device_t dev) {
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/* Rev B settings - FIXME: support other revs. */
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u32 dword = 0xA0E641E6;
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pci_write_config32(dev, 0x84, dword);
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dword = 0xE600A681;
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pci_write_config32(dev, 0x80, dword);
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}
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static void prep_fid_change(void)
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static void prep_fid_change(void)
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{
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{
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u32 dword;
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u32 dword;
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@ -295,12 +302,7 @@ static void prep_fid_change(void)
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config_nb_syn_ptr_adj(dev);
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config_nb_syn_ptr_adj(dev);
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/* Rev B settings - FIXME: support other revs. */
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config_acpi_pwr_state_ctrl_regs(dev);
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dword = 0xA0E641E6;
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pci_write_config32(dev, 0x84, dword);
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dword = 0xE600A681;
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pci_write_config32(dev, 0x80, dword);
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dword = pci_read_config32(dev, 0x80);
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dword = pci_read_config32(dev, 0x80);
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printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
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printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
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