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mainboard/google/zoombini/variant/meowth: enable speed shift 

BUG=b:73817825,b:69011806
BRANCH=master
TEST=Build and flash to meowth, verify cpufreq shows up in kernel
for all cores :

	localhost ~ # find / -name "cpufreq"
	/sys/devices/system/cpu/cpu3/cpufreq
	/sys/devices/system/cpu/cpu1/cpufreq
	/sys/devices/system/cpu/cpufreq
	/sys/devices/system/cpu/cpu2/cpufreq
	/sys/devices/system/cpu/cpu0/cpufreq
	/sys/module/cpufreq
	/usr/share/laptop-mode-tools/modules/cpufreq

Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/24902
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2018-02-27 10:30:34 -08:00 committed by Martin Roth
parent aef0d6b0a7
commit 4100f2b97c
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
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@ -70,6 +70,9 @@ chip soc/intel/cannonlake
register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp0" = "1"
register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkSsp1" = "1"
# Enable cpufreq
register "speed_shift_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device