x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commitbde6d30
(x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer), there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the Intel Ibex Peak SATA driver, fixed in commit9b5f137
(Intel ibexpeak: Fix SATA configuration). Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Reviewed-on: http://review.coreboot.org/8530 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -91,8 +91,8 @@ static void sc_enable_ioapic(struct device *dev)
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* Set SCI IRQ to IRQ9
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*/
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write32(ilb_base + ILB_OIC, 0x100); /* AEN */
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reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
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write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */
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reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
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write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
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*ioapic_index = 0;
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*ioapic_data = (1 << 25);
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@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
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reg32 &= ~(0xf << 28);
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reg32 |= (port << 28);
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reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
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write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
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write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
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}
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@ -11,7 +11,7 @@
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#include "amd8111.h"
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#define CMD3 (0x54/(sizeof(u32)))
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#define CMD3 0x54
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typedef enum {
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VAL3 = (1 << 31), /* VAL bit for byte 3 */
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@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev)
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
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volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
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u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
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u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
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/*
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* Enable ACPI I/O and power management.
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