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soc/intel/common/nvm: utilize spi_flash_ctrlr_protect_region() 

Now that there is spi flash controller flash protection use that API
so the spi_flash_protect() API can be sunsetted since it was isolated
within the Intel code base.

BUG=b:69614064

Change-Id: I3908d0e3105b0ef9a0fbf4fc9426ac1be067f648
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2017-12-14 16:14:39 -07:00
parent 10d65b06ae
commit 410f3b402a
1 changed files with 1 additions and 2 deletions
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3
src/soc/intel/common/nvm.c
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@ -22,7 +22,6 @@
#include <spi_flash.h> #include <spi_flash.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "nvm.h" #include "nvm.h"
#include "spi_flash.h"
/* Read flash status register to determine if write protect is active */ /* Read flash status register to determine if write protect is active */
int nvm_is_write_protected(void) int nvm_is_write_protected(void)
@ -62,5 +61,5 @@ int nvm_protect(const struct region *r)
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
return 0; return 0;
return spi_flash_protect(region_offset(r), region_sz(r)); return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r);
} }