soc/intel/cannonlake: Access conf pointer only if its not null
conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216 Reviewed-on: https://review.coreboot.org/c/30860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
parent
c896e92eaa
commit
41169def5c
|
@ -234,7 +234,7 @@ static void configure_isst(void)
|
|||
config_t *conf = dev->chip_info;
|
||||
msr_t msr;
|
||||
|
||||
if (conf->speed_shift_enable) {
|
||||
if (conf && conf->speed_shift_enable) {
|
||||
/*
|
||||
* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
|
||||
* is supported or not. coreboot needs to configure MSR 0x1AA
|
||||
|
@ -267,7 +267,7 @@ static void configure_misc(void)
|
|||
msr = rdmsr(IA32_MISC_ENABLE);
|
||||
msr.lo |= (1 << 0); /* Fast String enable */
|
||||
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
|
||||
if (conf->eist_enable)
|
||||
if (conf && conf->eist_enable)
|
||||
cpu_enable_eist();
|
||||
else
|
||||
cpu_disable_eist();
|
||||
|
|
Loading…
Reference in New Issue