mb/google/hatch: Make puff and variants share common ec.h
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
7896b8ce59
commit
4119616718
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* __BASEBOARD_EC_H__ */
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@ -3,57 +3,6 @@
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#include <puff/ec.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* VARIANT_EC_H */
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#endif
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@ -3,57 +3,6 @@
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#include <puff/ec.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* VARIANT_EC_H */
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#endif
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@ -3,57 +3,6 @@
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#include <puff/ec.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* VARIANT_EC_H */
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#endif
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@ -3,57 +3,6 @@
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#include <puff/ec.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* VARIANT_EC_H */
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#endif
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