src/mb/sifive/hifive-unleashed: replace fdt in maskrom
The fdt in the maskrom cannot be used to start linux. The correct fdt is dumped by replacing the bbl of the original firmware and used in coreboot. Correct the mac address in fdt by reading otp Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/31047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
This commit is contained in:
Xiang Wang
Patrick Georgi
parent
c6d672fe1d
commit
411a8b7a66
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@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_SIFIVE_FU540
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select BOARD_ROMSIZE_KB_32768
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select MISSING_BOARD_RESET
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select FLATTENED_DEVICE_TREE
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config HEAP_SIZE
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default 0x10000
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config MAINBOARD_DIR
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string
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@ -11,8 +11,20 @@
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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romstage-y += romstage.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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ramstage-y += fixup_fdt.c
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DTB=build/hifive-unleashed.dtb
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DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts
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$(DTB): $(DTS)
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dtc -I dts -O dtb -o $(DTB) $(DTS)
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cbfs-files-y += fallback/DTB
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fallback/DTB-file := $(DTB)
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fallback/DTB-type := raw
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@ -0,0 +1,105 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 HardenedLinux
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <soc/otp.h>
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#include <soc/sdram.h>
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#include <cbfs.h>
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#include <device_tree.h>
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#include <bootstate.h>
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#include <mcall.h>
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static void do_fixup_mac(struct device_tree_node *node)
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{
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uint32_t serial = otp_read_serial();
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static unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
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if (serial != ~0) {
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mac[5] |= (serial >> 0) & 0xff;
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mac[4] |= (serial >> 8) & 0xff;
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mac[3] |= (serial >> 16) & 0xff;
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}
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dt_add_bin_prop(node, "local-mac-address", mac, 6);
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}
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static void fixup_mac(struct device_tree_node *parent)
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{
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struct device_tree_property *prop;
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const char *name = "local-mac-address";
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list_for_each(prop, parent->properties, list_node) {
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if (!strcmp(name, prop->prop.name))
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do_fixup_mac(parent);
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}
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struct device_tree_node *child;
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list_for_each(child, parent->children, list_node) {
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fixup_mac(child);
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}
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}
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static void do_fixup_memory(struct device_tree_node *node)
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{
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u64 addrs[1], sizes[1];
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addrs[0] = 0x80000000;
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sizes[0] = sdram_size_mb() * 1024 * 1024;
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dt_add_reg_prop(node, addrs, sizes, 1, 2, 2);
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}
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static void fixup_memory(struct device_tree_node *parent)
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{
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struct device_tree_property *prop;
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const char *name = "device_type";
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const char *value = "memory";
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list_for_each(prop, parent->properties, list_node) {
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if (!strcmp(name, prop->prop.name)) {
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if (!strcmp(value, (char *)prop->prop.data))
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do_fixup_memory(parent);
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}
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}
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struct device_tree_node *child;
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list_for_each(child, parent->children, list_node) {
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fixup_memory(child);
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}
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}
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static void fixup_fdt(void *unused)
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{
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void *fdt_rom;
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struct device_tree *tree;
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/* load flat dt from cbfs */
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fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL);
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/* Expand DT into a tree */
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tree = fdt_unflatten(fdt_rom);
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/* fixup tree */
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fixup_mac(tree->root);
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fixup_memory(tree->root);
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/* convert the tree to a flat dt */
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void *dt = malloc(dt_flat_size(tree));
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dt_flatten(tree, dt);
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/* update HLS */
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for (int i = 0; i < CONFIG_MAX_CPUS; i++)
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OTHER_HLS(i)->fdt = dt;
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}
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BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, fixup_fdt, NULL);
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@ -0,0 +1,640 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 SiFive, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,fu540g", "sifive,fu500";
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model = "sifive,hifive-unleashed-a00";
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aliases {
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serial0 = &L28;
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serial1 = &L29;
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};
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chosen {
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};
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/*
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firmware {
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sifive,fsbl = "YYYY-MM-DD";
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};
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*/
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L3: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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L9: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&L24 &L0>;
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reg = <0>;
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riscv,isa = "rv64imac";
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sifive,dtim = <&L8>;
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sifive,itim = <&L7>;
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status = "okay";
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L10: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L12: cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L24 &L0>;
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reg = <1>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L11>;
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status = "okay";
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tlb-split;
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L13: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L15: cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L24 &L0>;
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reg = <2>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L14>;
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status = "okay";
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tlb-split;
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L16: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L18: cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L24 &L0>;
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reg = <3>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L17>;
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status = "okay";
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tlb-split;
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L19: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L21: cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L24 &L0>;
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reg = <4>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L20>;
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status = "okay";
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tlb-split;
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L22: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L36: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x00000000>;
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};
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L2: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
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ranges;
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refclk: refclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333333>;
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clock-output-names = "xtal";
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};
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prci: prci@10000000 {
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/* compatible = "sifive,ux00prci0"; */
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compatible = "sifive,aloeprci0";
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reg = <0x0 0x10000000 0x0 0x1000>;
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reg-names = "control";
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clocks = <&refclk>;
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#clock-cells = <1>;
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};
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tlclk: tlclk {
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compatible = "fixed-factor-clock";
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clocks = <&prci 0>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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L51: cadence-gemgxl-mgmt@100a0000 {
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compatible = "sifive,cadencegemgxlmgmt0";
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reg = <0x0 0x100a0000 0x0 0x1000>;
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reg-names = "control";
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#clock-cells = <0>;
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};
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L35: bus-blocker@100b8000 {
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compatible = "sifive,bus-blocker0";
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reg = <0x0 0x100b8000 0x0 0x1000>;
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reg-names = "control";
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};
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L0: cache-controller@2010000 {
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <2097152>;
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cache-unified;
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compatible = "sifive,ccache0", "cache";
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interrupt-parent = <&L4>;
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interrupts = <1 2 3>;
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next-level-cache = <&L25 &L40 &L36>;
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reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
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reg-names = "control", "sideband";
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};
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L33: cadence-ddr-mgmt@100c0000 {
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compatible = "sifive,cadenceddrmgmt0";
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reg = <0x0 0x100c0000 0x0 0x1000>;
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reg-names = "control";
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};
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L40: chiplink@40000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,chiplink", "simple-bus";
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ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>;
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};
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L5: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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reg-names = "control";
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};
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L6: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>;
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reg = <0x0 0x0 0x0 0x1000>;
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reg-names = "control";
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};
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L32: dma@3000000 {
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#dma-cells = <1>;
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compatible = "riscv,dma0";
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dma-channels = <4>;
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dma-requests = <0>;
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interrupt-parent = <&L4>;
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interrupts = <23 24 25 26 27 28 29 30>;
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reg = <0x0 0x3000000 0x0 0x100000>;
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reg-names = "control";
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riscv,dma-pools = <1>;
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};
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L8: dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x0 0x1000000 0x0 0x2000>;
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reg-names = "mem";
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};
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L44: ememoryotp@10070000 {
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compatible = "sifive,ememoryotp0";
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reg = <0x0 0x10070000 0x0 0x1000>;
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reg-names = "control";
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};
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L24: error-device@18000000 {
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compatible = "sifive,error0";
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reg = <0x0 0x18000000 0x0 0x8000000>;
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reg-names = "mem";
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};
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L52: ethernet@10090000 {
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compatible = "cdns,macb";
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interrupt-parent = <&L4>;
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interrupts = <53>;
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reg = <0x0 0x10090000 0x0 0x2000>;
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reg-names = "control";
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local-mac-address = [00 00 00 00 00 00];
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phy-mode = "gmii";
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&prci 1>, <&prci 1>, <&L51>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@0 {
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reg = <0>;
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reset-gpios = <&L31 12 1>;
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};
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};
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L31: gpio@10060000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <&L4>;
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interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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reg-names = "control";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&L31 10 1>;
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};
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L47: i2c@10030000 {
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||||
compatible = "sifive,i2c0", "opencores,i2c-ocores";
|
||||
reg = <0x0 0x10030000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* On pre-production boards only */
|
||||
/*
|
||||
ina233-vdd_soc_core@40 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x40>;
|
||||
};
|
||||
ina233-vdd_ddr_soc@44 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x44>;
|
||||
};
|
||||
ina233-vdd_ddr_mem@45 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x45>;
|
||||
};
|
||||
ina233-vdd_corepll@47 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x47>;
|
||||
};
|
||||
ina233-vdd_otp@4a {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
ina233-vdd_io@4b {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
ina233-vdd_ddrpll@48 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x48>;
|
||||
};
|
||||
ina233-avdd_ddrpll@49 {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x49>;
|
||||
};
|
||||
ina233-vdd_givdd@4c {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
ina233vdd_gemgxlpll@4d {
|
||||
compatible = "ti,pmbus";
|
||||
reg = <0x4d>;
|
||||
};
|
||||
*/
|
||||
/* On the tester board */
|
||||
/*
|
||||
m24c02 {
|
||||
compatible = "st,24c02";
|
||||
reg = <0x51>;
|
||||
};
|
||||
*/
|
||||
};
|
||||
L4: interrupt-controller@c000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,plic0";
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>;
|
||||
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||||
reg-names = "control";
|
||||
riscv,max-priority = <7>;
|
||||
riscv,ndev = <53>;
|
||||
};
|
||||
L7: itim@1800000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x0 0x1800000 0x0 0x4000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L11: itim@1808000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x0 0x1808000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L14: itim@1810000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x0 0x1810000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L17: itim@1818000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x0 0x1818000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L20: itim@1820000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x0 0x1820000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L37: memory-controller@100b0000 {
|
||||
/* compatible = "sifive,ux00ddr0"; */
|
||||
compatible = "sifive,aloeddr0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <31>;
|
||||
reg = <0x0 0x100b0000 0x0 0x4000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
pci@2000000000 {
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
device_type = "pci";
|
||||
interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <32>;
|
||||
ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
|
||||
reg = <0x020 0x0 0x0 0x4000000>;
|
||||
reg-names = "control";
|
||||
xil_pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
/*
|
||||
pci@2030000000 {
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
compatible = "ms-pf,axi-pcie-host";
|
||||
device_type = "pci";
|
||||
bus-range = <0x01 0x7f>;
|
||||
interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <32>;
|
||||
ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
|
||||
reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>;
|
||||
reg-names = "control", "apb";
|
||||
ms_pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
*/
|
||||
L53: pinctrl@10080000 {
|
||||
compatible = "sifive,pinctrl0";
|
||||
reg = <0x0 0x10080000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
L45: pwm@10020000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <42 43 44 45>;
|
||||
reg = <0x0 0x10020000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
sifive,approx-period = <1000000>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
L46: pwm@10021000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <46 47 48 49>;
|
||||
reg = <0x0 0x10021000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
sifive,approx-period = <1000000>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
heartbeat {
|
||||
pwms = <&L45 0 0>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
mtd {
|
||||
pwms = <&L45 1 0>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "mtd";
|
||||
};
|
||||
netdev {
|
||||
pwms = <&L45 2 0>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "netdev";
|
||||
};
|
||||
panic {
|
||||
pwms = <&L45 3 0>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "panic";
|
||||
};
|
||||
/* These LEDs are on the tester board */
|
||||
/*
|
||||
testled {
|
||||
pwms = <&L46 0 0>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
green {
|
||||
pwms = <&L46 1 0>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
red {
|
||||
pwms = <&L46 2 0>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
blue {
|
||||
pwms = <&L46 3 0>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
*/
|
||||
};
|
||||
L27: rom@1000 {
|
||||
compatible = "sifive,modeselect0";
|
||||
reg = <0x0 0x1000 0x0 0x1000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L26: rom@10000 {
|
||||
compatible = "sifive,maskrom0";
|
||||
reg = <0x0 0x10000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L25: rom@a000000 {
|
||||
compatible = "ucbbar,cacheable-zero0";
|
||||
reg = <0x0 0xa000000 0x0 0x2000000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L28: serial@10010000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <4>;
|
||||
reg = <0x0 0x10010000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
};
|
||||
L29: serial@10011000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <5>;
|
||||
reg = <0x0 0x10011000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
};
|
||||
L49: spi@10040000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <51>;
|
||||
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <&tlclk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp256d", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
L50: spi@10041000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <52>;
|
||||
reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <&tlclk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* These flash chips are on the tester board */
|
||||
/*
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp032", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
flash@1 {
|
||||
compatible = "issi,is25wp032", "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <25000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
flash@2 {
|
||||
compatible = "issi,is25wp032", "jedec,spi-nor";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <25000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
flash@3 {
|
||||
compatible = "issi,is25wp032", "jedec,spi-nor";
|
||||
reg = <3>;
|
||||
spi-max-frequency = <25000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
*/
|
||||
};
|
||||
L30: spi@10050000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <&L4>;
|
||||
interrupts = <6>;
|
||||
reg = <0x0 0x10050000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&tlclk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
disable-wp;
|
||||
gpios = <&L31 11 1>;
|
||||
};
|
||||
};
|
||||
L23: teststatus@4000 {
|
||||
compatible = "sifive,test0";
|
||||
reg = <0x0 0x4000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue