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siemens/mc_apl1: Correct GPIO settings 

- set GPIO_183 to high level for enabling the power of SD card
- delete all GPIOs for JTAG interface because they lead to problems with
  Lauterbach debug hardware

Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2017-05-08 12:49:58 +02:00 committed by Werner Zeh
parent 6c4e574872
commit 4125dde2be
2 changed files with 6 additions and 12 deletions
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5
src/mainboard/siemens/mc_apl1/brd_gpio.h
View File

@ -14,6 +14,9 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#ifndef _BRD_GPIO_H_
#define _BRD_GPIO_H_
#include <soc/gpio.h> #include <soc/gpio.h>
/* /*
@ -22,3 +25,5 @@
*/ */
const struct pad_config *brd_gpio_table(size_t *num); const struct pad_config *brd_gpio_table(size_t *num);
const struct pad_config *brd_early_gpio_table(size_t *num); const struct pad_config *brd_early_gpio_table(size_t *num);
#endif /* _BRD_GPIO_H_ */

13
src/mainboard/siemens/mc_apl1/gpio.c
View File

@ -69,7 +69,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */ PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */
/* SMBus */ /* SMBus */
PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */
@ -350,17 +350,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */ PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */
PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */ PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */
/* JTAG interface. */
PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* TCK */
PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* TRST_B */
PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), /* TMS */
PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), /* TDI */
PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), /* CX_PMODE */
PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), /* CX_PREQ_B */
PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), /* JTAGX */
PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), /* CX_PRDY_B */
PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), /* TDO */
/* CNV bridge described into IAFW Vol2. */ /* CNV bridge described into IAFW Vol2. */
/* GPIO_[216:219] described into EDS Vol1. */ /* GPIO_[216:219] described into EDS Vol1. */
PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */ PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */