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nvidia/ck804: Fix redundant configuration defines 

All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.

Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2015-02-03 08:05:55 +02:00
parent facf0b9361
commit 413e3da8c0
18 changed files with 30 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/nvidia/ck804/ac97.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,

7
src/southbridge/nvidia/ck804/bootblock.c
View File

@ -19,12 +19,7 @@
*/
#include <arch/io.h>
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#include "ck804.h"
static void ck804_enable_rom(void)
{

2
src/southbridge/nvidia/ck804/chip.h
View File

@ -31,4 +31,6 @@ struct southbridge_nvidia_ck804_config {
unsigned int mac_eeprom_addr;
};
extern struct pci_operations ck804_pci_ops;
#endif

4
src/southbridge/nvidia/ck804/ck804.c
View File

@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static u32 final_reg;
@ -57,7 +57,7 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn)
return lpc_dev;
}
void ck804_enable(device_t dev)
static void ck804_enable(device_t dev)
{
device_t lpc_dev;
unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;

14
src/southbridge/nvidia/ck804/ck804.h
View File

@ -21,10 +21,18 @@
#ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H
#define SOUTHBRIDGE_NVIDIA_CK804_CK804_H
#include "chip.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
void ck804_enable(device_t dev);
#define CK804B_BUSN 0x80
#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1)
extern struct pci_operations ck804_pci_ops;
#if CONFIG_CK804_NUM > 1
#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
#endif
#endif

21
src/southbridge/nvidia/ck804/early_setup.c
View File

@ -19,6 +19,7 @@
*/
#include <reset.h>
#include "ck804.h"
static int set_ht_link_ck804(u8 ht_c_num)
{
@ -66,28 +67,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
* 16 4 :4
*/
#if CONFIG_CK804_NUM > 1
#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
#ifndef CK804B_BUSN
#define CK804B_BUSN 0x80
#endif
#endif
#define CK804_CHIP_REV 3
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#endif
static void ck804_early_set_port(void)
{
static const unsigned int ctrl_devport_conf[] = {

14
src/southbridge/nvidia/ck804/early_setup_car.c
View File

@ -20,6 +20,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "ck804.h"
#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)
/* Someone messed up and snuck in some K8-specific code */
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
@ -73,18 +75,6 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_CHIP_REV 3
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#endif
static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
unsigned *io_base)
{

6
src/southbridge/nvidia/ck804/enable_usbdebug.c
View File

@ -30,12 +30,6 @@
#include <device/pci_def.h>
#include "ck804.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */

2
src/southbridge/nvidia/ck804/ht.c
View File

@ -23,8 +23,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include <arch/acpi.h>
#include "chip.h"
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)

2
src/southbridge/nvidia/ck804/ide.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static void ide_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/lpc.c
View File

@ -36,7 +36,7 @@
#include <stdlib.h>
#include <assert.h>
#include <cpu/amd/powernow.h>
#include "ck804.h"
#include "chip.h"
#define CK804_CHIP_REV 2

2
src/southbridge/nvidia/ck804/nic.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "ck804.h"
#include "chip.h"
static void nic_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/pci.c
View File

@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static void pci_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/pcie.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static void pcie_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/sata.c
View File

@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
#ifndef CK804_SATA_RESET_FOR_ATAPI
#define CK804_SATA_RESET_FOR_ATAPI 0

2
src/southbridge/nvidia/ck804/smbus.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ops.h>
#include <device/smbus.h>
#include <arch/io.h>
#include "ck804.h"
#include "chip.h"
#include "smbus.h"
static int lsmbus_recv_byte(device_t dev)

2
src/southbridge/nvidia/ck804/usb.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static void usb1_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/usb2.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "ck804.h"
#include "chip.h"
static void usb2_init(struct device *dev)
{