drivers/intel/fsp2_0: don't select FSP_USES_CB_STACK on FSP 2.0 platform

soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0
based, so it doesn't reuse coreboot's stack, but sets up its own stack.
In contrast to all other FSP 2.0 based platforms, this stack isn't in
the CAR region, since AMD Picasso doesn't support CAR and the DRAM is
already available when the x86 cores are released from reset. Selecting
FSP_USES_CB_STACK ended up doing the right thing, but is semantically
wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso
we take the corresponding code path if ENV_CACHE_AS_RAM is false which
is only the case for non-CAR platforms.

BUG=b:155501050
TEST=Timeless build results in an identical binary for amd/mandolin,
asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases
here.

Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/drivers/intel/fsp2_0/Kconfig

@@ -132,12 +132,14 @@ config FSP_USES_CB_STACK
 
 config FSP_TEMP_RAM_SIZE
 	hex
-	depends on FSP_USES_CB_STACK
 	help
-	  The amount of anticipated heap usage in CAR by FSP to setup HOB.
+	  The amount of memory coreboot reserves for the FSP to use. In the
-	  This configuration is applicable for FSP specification using shared
+	  case of FSP 2.1 and newer that share the stack with coreboot instead
-	  stack with coreboot/bootloader.
+	  of having its own stack, this is the amount of anticipated heap usage
-	  Sync this value with Platform FSP integration guide recommendation.
+	  in CAR by FSP to setup HOB and needs to be the recommended value from
+	  the Platform FSP integration guide. In the case of the FSP having its
+	  own stack that will be placed in DRAM and not in CAR, this is the
+	  amount of memory the FSP needs for its stack and heap.
 
 config FSP2_0_USES_TPM_MRC_HASH
 	bool

src/drivers/intel/fsp2_0/memory_init.c

@@ -184,8 +184,9 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
 	 * top and does not reinitialize stack pointer. The parameters passed
 	 * as StackBase and StackSize are actually for temporary RAM and HOBs
 	 * and are not related to FSP stack at all.
+	 * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack.
 	 */
-	if (CONFIG(FSP_USES_CB_STACK)) {
+	if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) {
 		arch_upd->StackBase = temp_ram;
 		arch_upd->StackSize = sizeof(temp_ram);
 	} else if (setup_fsp_stack_frame(arch_upd, memmap)) {

src/soc/amd/picasso/Kconfig

@@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select FSP_COMPRESS_FSP_M_LZMA
 	select FSP_COMPRESS_FSP_S_LZMA
-	select FSP_USES_CB_STACK
 	select UDK_2017_BINDING
 	select HAVE_CF9_RESET
 	select SUPPORT_CPU_UCODE_IN_CBFS
@@ -377,7 +376,6 @@ config MAINBOARD_POWER_RESTORE
 
 config FSP_TEMP_RAM_SIZE
 	hex
-	depends on FSP_USES_CB_STACK
 	default 0x40000
 	help
 	  The amount of coreboot-allocated heap and stack usage by the FSP.