From 416cc665929e4e66bcab3e395daa031401a61fe8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 31 Jan 2024 12:17:58 +0100 Subject: [PATCH] soc/amd: commonize PCI root IOAPIC initialization Make the initialization of the IOAPIC(s) in the PCI root(s) common across all AMD family 17h+ SoCs. For this the more general implementation from the Genoa code that supports multiple PC roots is moved to the common AMD code. All other family 17h+ SoCs are then adapted to use the common code. For those non-Genoa SoCs, the initialization of this second IOAPIC is moved from the northbridge device to the domain device above to match Genoa. Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized on Mandolin Signed-off-by: Felix Held Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chip.c | 2 ++ src/soc/amd/cezanne/root_complex.c | 6 ------ .../block/include/amdblocks/root_complex.h | 2 ++ .../amd/common/block/root_complex/Makefile.mk | 7 ++++++- src/soc/amd/common/block/root_complex/ioapic.c | 17 +++++++++++++++++ src/soc/amd/genoa_poc/domain.c | 11 +---------- src/soc/amd/glinda/chip.c | 2 ++ src/soc/amd/glinda/root_complex.c | 6 ------ src/soc/amd/mendocino/chip.c | 2 ++ src/soc/amd/mendocino/root_complex.c | 6 ------ src/soc/amd/phoenix/chip.c | 2 ++ src/soc/amd/phoenix/root_complex.c | 6 ------ src/soc/amd/picasso/chip.c | 2 ++ src/soc/amd/picasso/root_complex.c | 6 ------ 14 files changed, 36 insertions(+), 41 deletions(-) create mode 100644 src/soc/amd/common/block/root_complex/ioapic.c diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index ffbd94a404..7d315cbd3b 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,7 @@ struct device_operations cezanne_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 0fb086fc50..72a24199e2 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -42,11 +42,6 @@ struct dptc_input { }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_cezanne_config *config = config_of_soc(); @@ -76,7 +71,6 @@ struct device_operations cezanne_root_complex_operations = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h index cac659e756..767221ec06 100644 --- a/src/soc/amd/common/block/include/amdblocks/root_complex.h +++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h @@ -31,4 +31,6 @@ signed int get_iohc_fabric_id(struct device *domain); void read_fsp_resources(struct device *dev, unsigned long *idx); +void amd_pci_domain_init(struct device *domain); + #endif /* AMD_BLOCK_ROOT_COMPLEX_H */ diff --git a/src/soc/amd/common/block/root_complex/Makefile.mk b/src/soc/amd/common/block/root_complex/Makefile.mk index ba550bda6b..07f3ab108e 100644 --- a/src/soc/amd/common/block/root_complex/Makefile.mk +++ b/src/soc/amd/common/block/root_complex/Makefile.mk @@ -1,2 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX),y) + +ramstage-y += ioapic.c +ramstage-y += non_pci_resources.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c new file mode 100644 index 0000000000..cdeb53239b --- /dev/null +++ b/src/soc/amd/common/block/root_complex/ioapic.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void amd_pci_domain_init(struct device *domain) +{ + struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); + if (!res) + return; + + register_new_ioapic((void *)(uintptr_t)res->base); +} diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 711dfc3d79..14248cdda5 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -42,15 +42,6 @@ static void genoa_domain_set_resources(struct device *domain) } } -static void genoa_domain_init(struct device *domain) -{ - struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); - if (!res) - return; - - register_new_ioapic((void *)(uintptr_t)res->base); -} - static const char *genoa_domain_acpi_name(const struct device *domain) { const char *domain_acpi_names[4] = { @@ -70,7 +61,7 @@ struct device_operations genoa_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = genoa_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, - .init = genoa_domain_init, + .init = amd_pci_domain_init, .acpi_name = genoa_domain_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 13933c7df6..c8b4d082e0 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ struct device_operations glinda_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 36942bf1f2..d51fef2deb 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -57,11 +57,6 @@ struct dptc_input { }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_glinda_config *config = config_of_soc(); @@ -106,7 +101,6 @@ struct device_operations glinda_root_complex_operations = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 0bb963747b..99f57aa576 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,7 @@ struct device_operations mendocino_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 3247eb48f4..217983331f 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -85,11 +85,6 @@ struct dptc_input { }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_mendocino_config *config = config_of_soc(); @@ -267,7 +262,6 @@ struct device_operations mendocino_root_complex_operations = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index a9b0e571f1..b08db2b724 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,7 @@ struct device_operations phoenix_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 4ce5f2af34..918b7bd9bd 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -57,11 +57,6 @@ struct dptc_input { }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_phoenix_config *config = config_of_soc(); @@ -106,7 +101,6 @@ struct device_operations phoenix_root_complex_operations = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index d896a83372..d2070c13f8 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -30,6 +31,7 @@ struct device_operations picasso_pci_domain_ops = { .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = amd_pci_domain_scan_bus, + .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index d4e8401cae..dd39cb284b 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -42,11 +42,6 @@ struct dptc_input { }, \ } -static void root_complex_init(struct device *dev) -{ - register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); -} - static void acipgen_dptci(void) { const struct soc_amd_picasso_config *config = config_of_soc(); @@ -85,7 +80,6 @@ struct device_operations picasso_root_complex_operations = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, - .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, };