From 416ded8dc19ed91440536b4eac0d6fc5af60365a Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 23 Jan 2018 21:58:36 -0800 Subject: [PATCH] soc/intel/cannonlake: Add more HDA Audio Link settings Since FSP version 7.x.11.43, more HDA Audio link options are exposed, so included that into coreboot. Users can modify that base on platform implementations. BUG=None TEST=Boot up with debug build version FSP and check the debug print result on meowth platform. Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/23400 Tested-by: build bot (Jenkins) Reviewed-by: Sathyanarayana Nujella Reviewed-by: Nick Vaccaro --- src/soc/intel/cannonlake/chip.c | 9 +++++++++ src/soc/intel/cannonlake/chip.h | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 68f95d3df3..2187f906cf 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -215,6 +215,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; + params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; + params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; + params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; + params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; + params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; + params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; + params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; + params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; + params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0bbcdc44f3..5e70fae26f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -138,6 +138,15 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; + uint8_t PchHdaAudioLinkDmic0; + uint8_t PchHdaAudioLinkDmic1; + uint8_t PchHdaAudioLinkSsp0; + uint8_t PchHdaAudioLinkSsp1; + uint8_t PchHdaAudioLinkSsp2; + uint8_t PchHdaAudioLinkSndw1; + uint8_t PchHdaAudioLinkSndw2; + uint8_t PchHdaAudioLinkSndw3; + uint8_t PchHdaAudioLinkSndw4; /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];