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sb/intel/lynxpoint: Refactor usb_xhci_port_count_usb3

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Change the function parameters to avoid preprocessor usage.

Change-Id: Iec43e057ed2a629e702e0f484ff7f19fe8a0311b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2021-03-03 17:30:52 +01:00 committed by Patrick Georgi
parent b9338ba502
commit 418190cbba
1 changed files with 10 additions and 9 deletions
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19
src/southbridge/intel/lynxpoint/usb_xhci.c
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@ -28,18 +28,19 @@ static u8 *usb_xhci_mem_base(struct device *dev)
return (u8 *)(mem_base & ~0xf); return (u8 *)(mem_base & ~0xf);
} }
#ifdef __SIMPLE_DEVICE__ static int usb_xhci_port_count_usb3(u8 *mem_base)
static int usb_xhci_port_count_usb3(pci_devfn_t dev)
#else
static int usb_xhci_port_count_usb3(struct device *dev)
#endif
{ {
if (!mem_base) {
/* Do not proceed if BAR is invalid */
return 0;
}
if (pch_is_lp()) { if (pch_is_lp()) {
/* LynxPoint-LP has 4 SS ports */ /* LynxPoint-LP has 4 SS ports */
return 4; return 4;
} }
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
u8 *mem_base = usb_xhci_mem_base(dev); /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
u32 fus = read32(mem_base + XHCI_USB3FUS); u32 fus = read32(mem_base + XHCI_USB3FUS);
fus >>= XHCI_USB3FUS_SS_SHIFT; fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK; fus &= XHCI_USB3FUS_SS_MASK;
@ -87,10 +88,10 @@ static void usb_xhci_reset_usb3(struct device *dev, int all)
{ {
u32 status, port_disabled; u32 status, port_disabled;
int timeout, port; int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
u8 *mem_base = usb_xhci_mem_base(dev); u8 *mem_base = usb_xhci_mem_base(dev);
int port_count = usb_xhci_port_count_usb3(mem_base);
if (!mem_base || !port_count) if (!port_count)
return; return;
/* Get mask of disabled ports */ /* Get mask of disabled ports */