soc/intel/common/block/sata: Add common SATA driver

Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.

BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.

Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/sata/Kconfig

@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_SATA
+	bool
+	help
+	  Common SATA module for Intel PCH

src/soc/intel/common/block/sata/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c

src/soc/intel/common/block/sata/sata.c

@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void sata_final(struct device *dev)
+{
+	/* Set Bus Master */
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+}
+
+static struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.final			= sata_final,
+	.ops_pci		= &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_SPT_U_SATA,
+	PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA,
+	PCI_DEVICE_ID_INTEL_SPT_KBL_SATA,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_RAID,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_ALT,
+	PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT,
+	PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST,
+	PCI_DEVICE_ID_INTEL_CNL_SATA,
+	PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA,
+	PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA,
+	PCI_DEVICE_ID_INTEL_CNP_H_SATA,
+	PCI_DEVICE_ID_INTEL_CNP_LP_SATA,
+	PCI_DEVICE_ID_INTEL_ICP_U_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_LP_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_H_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA,
+	PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA,
+	PCI_DEVICE_ID_INTEL_TGP_LP_SATA,
+	PCI_DEVICE_ID_INTEL_TGP_SATA,
+	PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA,
+	PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA,
+	PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA,
+	PCI_DEVICE_ID_INTEL_JSP_SATA_1,
+	PCI_DEVICE_ID_INTEL_JSP_SATA_2,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_1,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_2,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_3,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_4,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_5,
+	PCI_DEVICE_ID_INTEL_ADP_P_SATA_6,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_1,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_2,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_3,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_4,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_5,
+	PCI_DEVICE_ID_INTEL_ADP_S_SATA_6,
+	0
+};
+
+static const struct pci_driver pch_sata __pci_driver = {
+	.ops     = &sata_ops,
+	.vendor  = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};

src/soc/intel/common/pch/Kconfig

@@ -32,6 +32,7 @@ config PCH_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_PCR
 	select SOC_INTEL_COMMON_BLOCK_PMC
 	select SOC_INTEL_COMMON_BLOCK_RTC
+	select SOC_INTEL_COMMON_BLOCK_SATA
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_BLOCK_TCO