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mb/google/poppy/variants/atlas: enable NVMe 

This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and
clock#4.

BUG=b:113369699
TEST=booted on atlas

Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Caveh Jalali 2018-09-06 19:55:21 -07:00 committed by Furquan Shaikh
parent dce4d465a6
commit 41979d862a
2 changed files with 18 additions and 4 deletions
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18
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -147,7 +147,7 @@ chip soc/intel/skylake
.dc_loadline = 441, .dc_loadline = 441,
}" }"
# PCIe Root port 1 with SRCCLKREQ1# # PCIe Root port 1 with SRCCLKREQ1# (WLAN)
register "PcieRpEnable[0]" = "1" register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[0]" = "1"
@ -155,6 +155,20 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1"
# PCIe Root port 5 (NVMe)
# PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ4#
# PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "4"
register "PcieRpClkSrcNumber[4]" = "4"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
# USB 2.0 # USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
@ -329,7 +343,7 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2 device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3 device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4 device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5 device pci 1c.4 on end # PCI Express Port 5 (NVMe)
device pci 1c.5 off end # PCI Express Port 6 device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7 device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8 device pci 1c.7 off end # PCI Express Port 8

4
src/mainboard/google/poppy/variants/atlas/gpio.c
View File

@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_B7), PAD_CFG_NC(GPP_B7),
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, RSMRST), PAD_CFG_GPO(GPP_B8, 0, RSMRST),
/* B9 : SRCCLKREQ4# ==> NC */ /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */
PAD_CFG_NC(GPP_B9), PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : SRCCLKREQ5# ==> NC */ /* B10 : SRCCLKREQ5# ==> NC */
PAD_CFG_NC(GPP_B10), PAD_CFG_NC(GPP_B10),
/* B11 : EXT_PWR_GATE# ==> NC */ /* B11 : EXT_PWR_GATE# ==> NC */