cpu/x86: Default to PARALLEL_MP selected

Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2021-05-29 21:23:18 +03:00
parent 8cc25d229f
commit 41a2c73b06
30 changed files with 15 additions and 26 deletions

View File

@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT #select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_MP
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_TIMEBASE
select HAVE_ASAN_IN_ROMSTAGE select HAVE_ASAN_IN_ROMSTAGE

View File

@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
config SMM_TSEG_SIZE config SMM_TSEG_SIZE
hex hex

View File

@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
config SMM_TSEG_SIZE config SMM_TSEG_SIZE
hex hex

View File

@ -15,10 +15,10 @@ choice
config CPU_QEMU_X86_LAPIC_INIT config CPU_QEMU_X86_LAPIC_INIT
bool "Legacy serial LAPIC init" bool "Legacy serial LAPIC init"
select LEGACY_SMP_INIT
config CPU_QEMU_X86_PARALLEL_MP config CPU_QEMU_X86_PARALLEL_MP
bool "Parallel MP init" bool "Parallel MP init"
select PARALLEL_MP
endchoice endchoice
@ -33,13 +33,13 @@ config CPU_QEMU_X86_NO_SMM
config CPU_QEMU_X86_ASEG_SMM config CPU_QEMU_X86_ASEG_SMM
bool "SMM in ASEG" bool "SMM in ASEG"
depends on !PARALLEL_MP depends on CPU_QEMU_X86_LAPIC_INIT
select SMM_ASEG select SMM_ASEG
config CPU_QEMU_X86_TSEG_SMM config CPU_QEMU_X86_TSEG_SMM
bool "SMM in TSEG" bool "SMM in TSEG"
select SMM_TSEG select SMM_TSEG
depends on PARALLEL_MP depends on CPU_QEMU_X86_PARALLEL_MP
endchoice endchoice

View File

@ -4,7 +4,9 @@ config PARALLEL_CPU_INIT
default n default n
config PARALLEL_MP config PARALLEL_MP
def_bool n def_bool y
depends on !LEGACY_SMP_INIT
depends on SMP
help help
This option uses common MP infrastructure for bringing up APs This option uses common MP infrastructure for bringing up APs
in parallel. It additionally provides a more flexible mechanism in parallel. It additionally provides a more flexible mechanism
@ -17,6 +19,9 @@ config PARALLEL_MP_AP_WORK
Allow APs to do other work after initialization instead of going Allow APs to do other work after initialization instead of going
to sleep. to sleep.
config LEGACY_SMP_INIT
bool
config UDELAY_LAPIC config UDELAY_LAPIC
bool bool
default n default n

View File

@ -2,6 +2,7 @@
config NORTHBRIDGE_AMD_AGESA_FAMILY14 config NORTHBRIDGE_AMD_AGESA_FAMILY14
bool bool
select LEGACY_SMP_INIT
select RESOURCE_ALLOCATOR_V3 select RESOURCE_ALLOCATOR_V3
if NORTHBRIDGE_AMD_AGESA_FAMILY14 if NORTHBRIDGE_AMD_AGESA_FAMILY14

View File

@ -2,6 +2,7 @@
config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
bool bool
select LEGACY_SMP_INIT
select RESOURCE_ALLOCATOR_V3 select RESOURCE_ALLOCATOR_V3
if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN

View File

@ -2,6 +2,7 @@
config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
bool bool
select LEGACY_SMP_INIT
select RESOURCE_ALLOCATOR_V3 select RESOURCE_ALLOCATOR_V3
if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB

View File

@ -2,6 +2,7 @@
config NORTHBRIDGE_AMD_PI_00730F01 config NORTHBRIDGE_AMD_PI_00730F01
bool bool
select LEGACY_SMP_INIT
if NORTHBRIDGE_AMD_PI_00730F01 if NORTHBRIDGE_AMD_PI_00730F01

View File

@ -10,5 +10,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE select NO_CBFS_MCACHE
select LEGACY_SMP_INIT
endif endif

View File

@ -12,7 +12,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
select INTEL_EDID select INTEL_EDID
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_GMA_SSC_ALTERNATE_REF
select PARALLEL_MP
config VBOOT config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_STARTS_IN_BOOTBLOCK

View File

@ -5,6 +5,7 @@ config NORTHBRIDGE_INTEL_I440BX
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE select NO_CBFS_MCACHE
select LEGACY_SMP_INIT
config SDRAMPWR_4DIMM config SDRAMPWR_4DIMM
bool bool

View File

@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_GMA_SSC_ALTERNATE_REF
select INTEL_EDID select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select PARALLEL_MP
config VBOOT config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_STARTS_IN_BOOTBLOCK

View File

@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select PARALLEL_MP
select NO_CBFS_MCACHE select NO_CBFS_MCACHE
config VGA_BIOS_ID config VGA_BIOS_ID

View File

@ -11,7 +11,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
select VGA select VGA
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select PARALLEL_MP
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
config CBFS_SIZE config CBFS_SIZE

View File

@ -28,7 +28,6 @@ config SOC_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE select IDT_IN_EVERY_STAGE
select IOAPIC select IOAPIC
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select PROVIDES_ROM_SHARING select PROVIDES_ROM_SHARING

View File

@ -57,7 +57,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_UCODE
select PROVIDES_ROM_SHARING select PROVIDES_ROM_SHARING
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select SSE2 select SSE2

View File

@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS select HAVE_USBDEBUG_OPTIONS
select IOAPIC select IOAPIC
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select RTC select RTC
select SOC_AMD_PI select SOC_AMD_PI

View File

@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_TME select INTEL_TME
select MP_SERVICES_PPI_V2 select MP_SERVICES_PPI_V2
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2 select PLATFORM_USES_FSP2_2

View File

@ -46,7 +46,6 @@ config CPU_SPECIFIC_OPTIONS
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select MRC_SETTINGS_VARIABLE_DATA select MRC_SETTINGS_VARIABLE_DATA
select NO_XIP_EARLY_STAGES select NO_XIP_EARLY_STAGES
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK

View File

@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
select PARALLEL_MP
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK
select REG_SCRIPT select REG_SCRIPT

View File

@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select PARALLEL_MP
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_CLK_PM select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK

View File

@ -68,7 +68,6 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC select IOAPIC
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select PM_ACPI_TIMER_OPTIONAL select PM_ACPI_TIMER_OPTIONAL

View File

@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FSP_REPO select HAVE_INTEL_FSP_REPO
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select PARALLEL_MP
select PCR_COMMON_IOSF_1_0 select PCR_COMMON_IOSF_1_0
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE

View File

@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC select IOAPIC
select MP_SERVICES_PPI_V1 select MP_SERVICES_PPI_V1
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1 select PLATFORM_USES_FSP2_1

View File

@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC select IOAPIC
select MP_SERVICES_PPI_V1 select MP_SERVICES_PPI_V1
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1 select PLATFORM_USES_FSP2_1

View File

@ -29,7 +29,6 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC select IOAPIC
select MP_SERVICES_PPI_V1 select MP_SERVICES_PPI_V1
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2 select PLATFORM_USES_FSP2_2

View File

@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC select IOAPIC
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select PM_ACPI_TIMER_OPTIONAL select PM_ACPI_TIMER_OPTIONAL

View File

@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC select IOAPIC
select MP_SERVICES_PPI_V1 select MP_SERVICES_PPI_V1
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2 select PLATFORM_USES_FSP2_2

View File

@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
select FSP_M_XIP select FSP_M_XIP
select POSTCAR_STAGE select POSTCAR_STAGE
select IOAPIC select IOAPIC
select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_GLOBAL_RESET_ENABLE_LOCK
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE