mb/razer/blade_stealth_kbl: Remove comments with pad functions
Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have. Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Maxim Polyakov
Patrick Georgi
parent
64ab189a65
commit
41a36a3d3e
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@ -22,158 +22,156 @@
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||||||
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/* Pad configuration in ramstage. */
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/* Pad configuration in ramstage. */
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||||||
static const struct pad_config gpio_table[] = {
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static const struct pad_config gpio_table[] = {
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||||||
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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||||||
/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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||||||
/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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||||||
/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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||||||
/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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||||||
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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||||||
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
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||||||
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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||||||
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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||||||
/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP),
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PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK),
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PAD_CFG_GPO(GPP_A12, 1, PWROK),
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||||||
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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||||||
/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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||||||
/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
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||||||
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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||||||
/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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||||||
/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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||||||
/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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||||||
/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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||||||
/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
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PAD_CFG_GPO(GPP_A22, 1, DEEP),
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||||||
/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP),
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PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP),
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||||||
/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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||||||
/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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||||||
/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
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PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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||||||
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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||||||
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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||||||
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_NC(GPP_B8, NONE),
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PAD_NC(GPP_B8, NONE),
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||||||
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_NC(GPP_B10, NONE),
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PAD_NC(GPP_B10, NONE),
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||||||
/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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||||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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||||||
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
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PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP),
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PAD_CFG_GPO(GPP_B15, 0, DEEP),
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||||||
/* GPIO */ PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B16, NONE),
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||||||
/* GPIO */ PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT),
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PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT),
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||||||
/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
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||||||
/* GPIO */ PAD_NC(GPP_B19, NONE),
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PAD_NC(GPP_B19, NONE),
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||||||
/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
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||||||
/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
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||||||
/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
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PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
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||||||
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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||||||
/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
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PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
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||||||
/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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||||||
/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
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PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
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||||||
/* GPP_C6 - RESERVED */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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||||||
/* GPP_C7 - RESERVED */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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||||||
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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||||||
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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||||||
/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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||||||
/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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||||||
/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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||||||
/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
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||||||
/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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||||||
/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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||||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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||||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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||||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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||||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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||||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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||||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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||||||
/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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||||||
/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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||||||
/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
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||||||
/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
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||||||
/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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||||||
/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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||||||
/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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||||||
/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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||||||
/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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||||||
/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
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||||||
/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
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||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
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||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
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||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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||||||
/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
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||||||
/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
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||||||
/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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||||||
/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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||||||
/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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||||||
/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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||||||
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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||||||
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
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||||||
/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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||||||
/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
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PAD_CFG_GPI_SCI(GPP_E0, NONE, DEEP, EDGE_SINGLE, INVERT),
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||||||
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_SCI(GPP_E0, NONE, DEEP, EDGE_SINGLE, INVERT),
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PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
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||||||
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI),
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||||||
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
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||||||
/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
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||||||
/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
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PAD_CFG_GPO(GPP_E6, 0, DEEP),
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||||||
/* GPIO */ PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
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PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
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PAD_CFG_GPO(GPP_E9, 0, DEEP),
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||||||
/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
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||||||
/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP),
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PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
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||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
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PAD_NC(GPP_E12, NONE),
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||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_NC(GPP_E12, NONE),
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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||||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
|
||||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
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||||||
/* GPIO */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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||||||
/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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||||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
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||||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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||||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
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||||||
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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PAD_CFG_GPI_APIC_LOW(GPP_E22, NONE, DEEP),
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||||||
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
|
PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
|
||||||
/* GPIO */ PAD_CFG_GPI_APIC_LOW(GPP_E22, NONE, DEEP),
|
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||||
/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
|
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||||
/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||||
/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
||||||
/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
|
||||||
/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
|
||||||
/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
|
||||||
/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
|
||||||
/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||||
/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||||
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2),
|
||||||
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2),
|
||||||
/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2),
|
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||||
/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2),
|
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
|
||||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
|
||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
|
||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
|
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
|
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
|
||||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||||
/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
|
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI),
|
||||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
|
||||||
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif /* __ACPI__ */
|
#endif /* __ACPI__ */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue