soc/intel/common/block: Update SA resource length to support 64 bit

This patch provides an option for accommodating 64 bit width resource
request with CONFIG_PCI_SEGMENT_GROUPS = 16 refer as PCIEX BAR length 4096MB
(Bus 0-4095).

Change-Id: I9a8448af7e9f26c8e0176e58e4fe253a6e77b69a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40336
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/include/intelblocks/systemagent.h

@@ -31,13 +31,13 @@ void bootblock_systemagent_early_init(void);
  *   INDEX = Either PCI configuration space registers or MMIO offsets
  *   mapped from REG.
  *   BASE = 64 bit Address.
- *   SIZE = base length
+ *   SIZE = 64 bit base length
  *   DESCRIPTION = Name of the register/offset.
  */
 struct sa_mmio_descriptor {
 	unsigned int index;
 	uint64_t base;
-	size_t size;
+	uint64_t size;
 	const char *description;
 };