GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/baytrail/lpss.c: Align with Braswell 

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-07 17:54:56 +02:00
parent 12baf2057c
commit 41b1edf58b
1 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/soc/intel/baytrail/lpss.c
View File

@ -15,16 +15,15 @@
#include "chip.h" #include "chip.h"
static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
int nvs_index)
{ {
struct reg_script ops[] = { struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */ /* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND, REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
/* Enable ACPI mode */ /* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
REG_SCRIPT_END REG_SCRIPT_END
}; };
struct resource *bar; struct resource *bar;
@ -63,14 +62,17 @@ static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
reg_script_run_on_dev(dev, ops); reg_script_run_on_dev(dev, ops);
} }
#define SET_IOSF_REG(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
do { \
*iosf_reg = LPSS_ ## name_ ## _CTL; \
*nvs_index = LPSS_NVS_ ## name_; \
} while (0)
static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{ {
*iosf_reg = -1; *iosf_reg = -1;
*nvs_index = -1; *nvs_index = -1;
#define SET_IOSF_REG(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
*iosf_reg = LPSS_ ## name_ ## _CTL; \
*nvs_index = LPSS_NVS_ ## name_
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
SET_IOSF_REG(SIO_DMA1); SET_IOSF_REG(SIO_DMA1);
@ -104,6 +106,8 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
} }
} }
#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
static void i2c_disable_resets(struct device *dev) static void i2c_disable_resets(struct device *dev)
{ {
/* Release the I2C devices from reset. */ /* Release the I2C devices from reset. */
@ -112,9 +116,6 @@ static void i2c_disable_resets(struct device *dev)
REG_SCRIPT_END, REG_SCRIPT_END,
}; };
#define CASE_I2C(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
CASE_I2C(I2C1): CASE_I2C(I2C1):
CASE_I2C(I2C2): CASE_I2C(I2C2):
@ -141,8 +142,7 @@ static void lpss_init(struct device *dev)
if (iosf_reg < 0) { if (iosf_reg < 0) {
int slot = PCI_SLOT(dev->path.pci.devfn); int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn);
printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func);
slot, func);
return; return;
} }
dev_enable_snoop_and_pm(dev, iosf_reg); dev_enable_snoop_and_pm(dev, iosf_reg);