AGESA f14: Factor out default MTRR settings
All AGESA f14 boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Id980e4671e51fe800188f0a84768a307c8965886 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
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@ -83,7 +83,6 @@
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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@ -157,23 +156,6 @@
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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@ -83,7 +83,6 @@
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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@ -157,23 +156,6 @@
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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@ -83,7 +83,6 @@
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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@ -62,23 +62,6 @@
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* needed by the system.
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*/
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
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{ CPU_LIST_TERMINAL }
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};
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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
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@ -108,7 +91,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* Include the files that instantiate the configuration definitions. */
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#include "cpuRegisters.h"
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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* needed by the system.
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*/
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/* The fixed MTRR values to be set after memory initialization. */
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const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/* MEMORY_BUS_SPEED */
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#define DDR400_FREQUENCY 200 /**< DDR 400 */
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#define DDR533_FREQUENCY 266 /**< DDR 533 */
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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*/
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#include <AGESA.h>
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/* The fixed MTRR values to be set after memory initialization. */
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CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
|
|
|
@ -83,7 +83,6 @@
|
|||
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
|
||||
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
|
||||
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||
#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
//#define BLDCFG_STARTING_BUSNUM 0
|
||||
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
|
||||
|
@ -157,23 +156,6 @@
|
|||
*/
|
||||
#include <AGESA.h>
|
||||
|
||||
/* The fixed MTRR values to be set after memory initialization. */
|
||||
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
|
|
|
@ -83,7 +83,6 @@
|
|||
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
|
||||
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
|
||||
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||
#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
//#define BLDCFG_STARTING_BUSNUM 0
|
||||
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
|
||||
|
@ -157,23 +156,6 @@
|
|||
*/
|
||||
#include <AGESA.h>
|
||||
|
||||
/* The fixed MTRR values to be set after memory initialization. */
|
||||
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
|
|
|
@ -65,6 +65,23 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
NULL
|
||||
};
|
||||
|
||||
/* The default fixed MTRR values to be set after memory initialization */
|
||||
static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ CPU_LIST_TERMINAL },
|
||||
};
|
||||
|
||||
/* Process solution defined socket / family installations
|
||||
*
|
||||
* As part of the release package for each image, define the options below to select the
|
||||
|
@ -1079,7 +1096,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
|
|||
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
|
||||
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
|
||||
#else
|
||||
#define CFG_AP_MTRR_SETTINGS_LIST (NULL)
|
||||
#define CFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList)
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
|
|
Loading…
Reference in New Issue