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soc/amd/mendocino: Use common fsp-s preloader 

Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2023-01-11 15:11:08 -05:00 committed by Felix Held
parent 16f55f237c
commit 41c7e31b0a
3 changed files with 1 additions and 14 deletions
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1
src/soc/amd/mendocino/Kconfig
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@ -72,6 +72,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2 select SSE2
select UDK_2017_BINDING select UDK_2017_BINDING
select USE_DDR5 select USE_DDR5

1
src/soc/amd/mendocino/Makefile.inc
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@ -39,7 +39,6 @@ ramstage-y += fsp_s_params.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += i2c.c ramstage-y += i2c.c
ramstage-y += mca.c ramstage-y += mca.c
ramstage-y += preload.c
ramstage-y += reset.c ramstage-y += reset.c
ramstage-y += root_complex.c ramstage-y += root_complex.c
ramstage-y += uart.c ramstage-y += uart.c

13
src/soc/amd/mendocino/preload.c
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */
#include <bootstate.h>
#include <fsp/api.h>
static void start_fsps_preload(void *unused)
{
preload_fsps();
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);