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cpu/x86/lapic: Regroup LAPIC accessors 

Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55186
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-05-31 12:38:41 +03:00
parent b89832ac6a
commit 41e6216df3
1 changed files with 63 additions and 43 deletions
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106
src/include/cpu/x86/lapic.h
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@ -8,6 +8,61 @@
#include <halt.h> #include <halt.h>
#include <stdint.h> #include <stdint.h>
static __always_inline uint32_t xapic_read(unsigned int reg)
{
return read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg));
}
static __always_inline void xapic_write(unsigned int reg, uint32_t v)
{
write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v);
}
static inline void xapic_write_atomic(unsigned long reg, uint32_t v)
{
volatile uint32_t *ptr;
ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg);
asm volatile ("xchgl %0, %1\n"
: "+r" (v), "+m" (*(ptr))
: : "memory", "cc");
}
#define lapic_read_around(x) lapic_read(x)
#define lapic_write_around(x, y) xapic_write_atomic((x), (y))
static __always_inline uint32_t x2apic_read(unsigned int reg)
{
uint32_t value, index;
msr_t msr;
index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4);
msr = rdmsr(index);
value = msr.lo;
return value;
}
static __always_inline void x2apic_write(unsigned int reg, uint32_t v)
{
uint32_t index;
msr_t msr;
index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4);
msr.hi = 0x0;
msr.lo = v;
wrmsr(index, msr);
}
static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid)
{
msr_t icr;
icr.hi = apicid;
icr.lo = icrlow;
wrmsr(X2APIC_MSR_ICR_ADDRESS, icr);
}
static inline bool is_x2apic_mode(void) static inline bool is_x2apic_mode(void)
{ {
if (CONFIG(XAPIC_ONLY)) if (CONFIG(XAPIC_ONLY))
@ -21,41 +76,20 @@ static inline bool is_x2apic_mode(void)
return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED); return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED);
} }
static inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid)
{
msr_t icr;
icr.hi = apicid;
icr.lo = icrlow;
wrmsr(X2APIC_MSR_ICR_ADDRESS, icr);
}
static __always_inline uint32_t lapic_read(unsigned int reg) static __always_inline uint32_t lapic_read(unsigned int reg)
{ {
uint32_t value, index; if (is_x2apic_mode())
msr_t msr; return x2apic_read(reg);
else
if (is_x2apic_mode()) { return xapic_read(reg);
index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4);
msr = rdmsr(index);
value = msr.lo;
} else {
value = read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg));
}
return value;
} }
static __always_inline void lapic_write(unsigned int reg, uint32_t v) static __always_inline void lapic_write(unsigned int reg, uint32_t v)
{ {
msr_t msr; if (is_x2apic_mode())
uint32_t index; x2apic_write(reg, v);
if (is_x2apic_mode()) { else
index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); xapic_write(reg, v);
msr.hi = 0x0;
msr.lo = v;
wrmsr(index, msr);
} else {
write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v);
}
} }
static __always_inline void lapic_wait_icr_idle(void) static __always_inline void lapic_wait_icr_idle(void)
@ -115,20 +149,6 @@ static __always_inline void stop_this_cpu(void)
void stop_this_cpu(void); void stop_this_cpu(void);
#endif #endif
static inline void lapic_write_atomic(unsigned long reg, uint32_t v)
{
volatile uint32_t *ptr;
ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg);
asm volatile ("xchgl %0, %1\n"
: "+r" (v), "+m" (*(ptr))
: : "memory", "cc");
}
# define lapic_read_around(x) lapic_read(x)
# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
void lapic_virtual_wire_mode_init(void); void lapic_virtual_wire_mode_init(void);
/* See if I need to initialize the local APIC */ /* See if I need to initialize the local APIC */