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mb/google/octopus: Create Lick variant 

Create new variant for Lick that is copied from phaser variant.
Remove unnecessary code, due to not support touchscreen and stylus.
Set to default_override_table.
Remove variant.c.

BUG=b:145181137
BRANCH=octopus
TEST=./util/abuild/abuild -p none -t google/octopus -x -a

Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174
Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hash.Hung 2019-11-26 23:36:40 +08:00 committed by Patrick Georgi
parent afd687f71f
commit 41fe62b6dc
8 changed files with 234 additions and 0 deletions
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2
src/mainboard/google/octopus/Kconfig
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@ -63,6 +63,7 @@ config VARIANT_DIR
default "octopus" if BOARD_GOOGLE_OCTOPUS
default "garg" if BOARD_GOOGLE_GARG
default "dood" if BOARD_GOOGLE_DOOD
default "lick" if BOARD_GOOGLE_LICK
config DEVICETREE
string
@ -85,6 +86,7 @@ config MAINBOARD_PART_NUMBER
default "Octopus" if BOARD_GOOGLE_OCTOPUS
default "Garg" if BOARD_GOOGLE_GARG
default "Dood" if BOARD_GOOGLE_DOOD
default "Lick" if BOARD_GOOGLE_LICK
config MAINBOARD_FAMILY
string

6
src/mainboard/google/octopus/Kconfig.name
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@ -17,6 +17,12 @@ config BOARD_GOOGLE_PHASER
select BOARD_GOOGLE_BASEBOARD_OCTOPUS
select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
config BOARD_GOOGLE_LICK
bool "-> Lick"
select BASEBOARD_OCTOPUS_LAPTOP
select BOARD_GOOGLE_BASEBOARD_OCTOPUS
select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
config BOARD_GOOGLE_FLEEX
bool "-> Fleex"
select BASEBOARD_OCTOPUS_LAPTOP

3
src/mainboard/google/octopus/variants/lick/Makefile.inc Normal file
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@ -0,0 +1,3 @@
bootblock-y += gpio.c
ramstage-y += gpio.c

52
src/mainboard/google/octopus/variants/lick/gpio.c Normal file
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@ -0,0 +1,52 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
#define SKU_UNKNOWN 0xFFFFFFFF
static const struct pad_config default_override_table[] = {
/* disable I2C7 SCL and SDA */
PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */
PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */
PAD_NC(GPIO_52, UP_20K),
PAD_NC(GPIO_53, UP_20K),
PAD_NC(GPIO_67, UP_20K),
PAD_NC(GPIO_117, UP_20K),
PAD_NC(GPIO_143, UP_20K),
/* EN_PP3300_TOUCHSCREEN */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),
PAD_NC(GPIO_161, DN_20K),
/* EN_PP3300_WLAN_L */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),
PAD_NC(GPIO_213, DN_20K),
PAD_NC(GPIO_214, DN_20K),
};
const struct pad_config *variant_override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(default_override_table);
return default_override_table;
}

16
src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl Normal file
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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

21
src/mainboard/google/octopus/variants/lick/include/variant/ec.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif

21
src/mainboard/google/octopus/variants/lick/include/variant/gpio.h Normal file
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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <baseboard/gpio.h>
#endif /* MAINBOARD_GPIO_H */

113
src/mainboard/google/octopus/variants/lick/overridetree.cb Normal file
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@ -0,0 +1,113 @@
chip soc/intel/apollolake
# EMMC Tx CMD Delay
# Refer to EDS-Vol2-16.32.
# [14:8] steps of delay for DDR mode, each 125ps.
# [6:0] steps of delay for SDR mode, each 125ps.
register "emmc_tx_cmd_cntl" = "0x505"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-16.33.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0b0c"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-16.34.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x1c282929"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-16.35.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181b1b"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-16.37.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10028"
# EMMC Rx Strobe Delay
# Refer to EDS-Vol2-16.36.
# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
register "emmc_rx_strobe_cntl" = "0x0b0b"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C5 | Audio |
#| I2C6 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[6] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 66,
.fall_time_ns = 90,
.data_hold_time_ns = 350,
},
}"
device domain 0 on
device pci 17.1 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end # - I2C 5
device pci 17.2 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
register "wake" = "GPE0_DW3_27"
register "probed" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
register "generic.wake" = "GPE0_DW3_27"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 0x2c on end
end
end # - I2C 6
end
end