tegra132: Add support for tegra132 soc
Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Reviewed-on: http://review.coreboot.org/8040 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
Marc Jones
parent
17b9c198e0
commit
4208e0c834
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@ -1 +1,2 @@
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source src/soc/nvidia/tegra124/Kconfig
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source src/soc/nvidia/tegra132/Kconfig
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@ -1 +1,2 @@
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subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124
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subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132
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@ -0,0 +1,24 @@
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config SOC_NVIDIA_TEGRA132
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_ROMSTAGE_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select ARM_LPAE
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select DYNAMIC_CBMEM
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if SOC_NVIDIA_TEGRA132
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x18000
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config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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default 0x18080
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endif
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@ -0,0 +1,12 @@
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bootblock-y += cbfs.c
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bootblock-y += timer.c
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romstage-y += cbfs.c
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romstage-y += cbmem.c
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romstage-y += timer.c
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ramstage-y += cbfs.c
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ramstage-y += cbmem.c
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ramstage-y += timer.c
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CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cbfs.h> /* This driver serves as a CBFS media source. */
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int init_default_cbfs_media(struct cbfs_media *media)
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{
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return 0;
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cbmem.h>
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void *cbmem_top(void)
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{
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/* TODO: update with real cbmem_top function. */
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return NULL;
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}
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@ -0,0 +1,31 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__
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#define __SOC_NVIDIA_TEGRA132_CHIP_H__
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#include <arch/cache.h>
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#include <soc/addressmap.h>
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#define EFAULT 1
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#define EINVAL 2
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struct soc_nvidia_tegra132_config {
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};
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#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright 2014 Google Inc.
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*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__
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#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__
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#include <stddef.h>
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enum {
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TEGRA_SRAM_BASE = 0x40000000,
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TEGRA_SRAM_SIZE = 0x40000
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};
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enum {
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TEGRA_ARM_PERIPHBASE = 0x50040000,
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TEGRA_ARM_DISPLAYA = 0x54200000,
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TEGRA_ARM_DISPLAYB = 0x54240000,
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TEGRA_ARM_SOR = 0x54540000,
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TEGRA_ARM_DPAUX = 0x545c0000,
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TEGRA_PG_UP_BASE = 0x60000000,
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TEGRA_TMRUS_BASE = 0x60005010,
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TEGRA_CLK_RST_BASE = 0x60006000,
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TEGRA_FLOW_BASE = 0x60007000,
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TEGRA_GPIO_BASE = 0x6000D000,
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TEGRA_EVP_BASE = 0x6000F000,
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TEGRA_APB_DMA_BASE = 0x60020000,
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TEGRA_APB_MISC_BASE = 0x70000000,
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TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800,
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TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868,
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TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000,
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TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000,
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TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040,
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TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200,
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TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
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TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
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TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
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TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000,
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TEGRA_I2C_BASE = TEGRA_APB_MISC_BASE + 0xC000,
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TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
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TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400,
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TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500,
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TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700,
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TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000,
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TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100,
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TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
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TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
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TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
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TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00,
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TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00,
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TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00,
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TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
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TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
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TEGRA_MC_BASE = 0x70019000,
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TEGRA_EMC_BASE = 0x7001B000,
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TEGRA_CSITE_BASE = 0x70040000,
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TEGRA_SYSCTR0_BASE = 0x700F0000,
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TEGRA_USBD_BASE = 0x7D000000,
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TEGRA_USB2_BASE = 0x7D004000,
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TEGRA_USB3_BASE = 0x7D008000,
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};
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enum {
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TEGRA_I2C_BASE_COUNT = 6,
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};
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#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */
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@ -0,0 +1,276 @@
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/*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__
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#define __SOC_NVIDIA_TEGRA132_CLOCK_H__
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#include <stdint.h>
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enum {
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CLK_L_CPU = 0x1 << 0,
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CLK_L_COP = 0x1 << 1,
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CLK_L_TRIG_SYS = 0x1 << 2,
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CLK_L_RTC = 0x1 << 4,
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CLK_L_TMR = 0x1 << 5,
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CLK_L_UARTA = 0x1 << 6,
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CLK_L_UARTB = 0x1 << 7,
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CLK_L_GPIO = 0x1 << 8,
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CLK_L_SDMMC2 = 0x1 << 9,
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CLK_L_SPDIF = 0x1 << 10,
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CLK_L_I2S1 = 0x1 << 11,
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CLK_L_I2C1 = 0x1 << 12,
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CLK_L_NDFLASH = 0x1 << 13,
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CLK_L_SDMMC1 = 0x1 << 14,
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CLK_L_SDMMC4 = 0x1 << 15,
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CLK_L_PWM = 0x1 << 17,
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CLK_L_I2S2 = 0x1 << 18,
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CLK_L_EPP = 0x1 << 19,
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CLK_L_VI = 0x1 << 20,
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CLK_L_2D = 0x1 << 21,
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CLK_L_USBD = 0x1 << 22,
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CLK_L_ISP = 0x1 << 23,
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CLK_L_3D = 0x1 << 24,
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CLK_L_DISP2 = 0x1 << 26,
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CLK_L_DISP1 = 0x1 << 27,
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CLK_L_HOST1X = 0x1 << 28,
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CLK_L_VCP = 0x1 << 29,
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CLK_L_I2S0 = 0x1 << 30,
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CLK_L_CACHE2 = 0x1 << 31,
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CLK_H_MEM = 0x1 << 0,
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CLK_H_AHBDMA = 0x1 << 1,
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CLK_H_APBDMA = 0x1 << 2,
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CLK_H_KBC = 0x1 << 4,
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CLK_H_STAT_MON = 0x1 << 5,
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CLK_H_PMC = 0x1 << 6,
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CLK_H_FUSE = 0x1 << 7,
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CLK_H_KFUSE = 0x1 << 8,
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CLK_H_SBC1 = 0x1 << 9,
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CLK_H_SNOR = 0x1 << 10,
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CLK_H_JTAG2TBC = 0x1 << 11,
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CLK_H_SBC2 = 0x1 << 12,
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CLK_H_SBC3 = 0x1 << 14,
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CLK_H_I2C5 = 0x1 << 15,
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CLK_H_DSI = 0x1 << 16,
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CLK_H_HSI = 0x1 << 18,
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CLK_H_HDMI = 0x1 << 19,
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CLK_H_CSI = 0x1 << 20,
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CLK_H_I2C2 = 0x1 << 22,
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CLK_H_UARTC = 0x1 << 23,
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CLK_H_MIPI_CAL = 0x1 << 24,
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CLK_H_EMC = 0x1 << 25,
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CLK_H_USB2 = 0x1 << 26,
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CLK_H_USB3 = 0x1 << 27,
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CLK_H_MPE = 0x1 << 28,
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CLK_H_VDE = 0x1 << 29,
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CLK_H_BSEA = 0x1 << 30,
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CLK_H_BSEV = 0x1 << 31,
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CLK_U_UARTD = 0x1 << 1,
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CLK_U_UARTE = 0x1 << 2,
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CLK_U_I2C3 = 0x1 << 3,
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CLK_U_SBC4 = 0x1 << 4,
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CLK_U_SDMMC3 = 0x1 << 5,
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CLK_U_PCIE = 0x1 << 6,
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CLK_U_OWR = 0x1 << 7,
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CLK_U_AFI = 0x1 << 8,
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CLK_U_CSITE = 0x1 << 9,
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CLK_U_PCIEXCLK = 0x1 << 10,
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CLK_U_AVPUCQ = 0x1 << 11,
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CLK_U_TRACECLKIN = 0x1 << 13,
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CLK_U_SOC_THERM = 0x1 << 14,
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CLK_U_DTV = 0x1 << 15,
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CLK_U_NAND_SPEED = 0x1 << 16,
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CLK_U_I2C_SLOW = 0x1 << 17,
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CLK_U_DSIB = 0x1 << 18,
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CLK_U_TSEC = 0x1 << 19,
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CLK_U_IRAMA = 0x1 << 20,
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CLK_U_IRAMB = 0x1 << 21,
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CLK_U_IRAMC = 0x1 << 22,
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// Clock reset.
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CLK_U_EMUCIF = 0x1 << 23,
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// Clock enable.
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CLK_U_IRAMD = 0x1 << 23,
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CLK_U_CRAM2 = 0x2 << 24,
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CLK_U_XUSB_HOST = 0x1 << 25,
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CLK_U_MSENC = 0x1 << 27,
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CLK_U_SUS_OUT = 0x1 << 28,
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CLK_U_DEV2_OUT = 0x1 << 29,
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CLK_U_DEV1_OUT = 0x1 << 30,
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CLK_U_XUSB_DEV = 0x1 << 31,
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CLK_V_CPUG = 0x1 << 0,
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CLK_V_CPULP = 0x1 << 1,
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CLK_V_3D2 = 0x1 << 2,
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CLK_V_MSELECT = 0x1 << 3,
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CLK_V_I2S3 = 0x1 << 5,
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CLK_V_I2S4 = 0x1 << 6,
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CLK_V_I2C4 = 0x1 << 7,
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CLK_V_SBC5 = 0x1 << 8,
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CLK_V_SBC6 = 0x1 << 9,
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CLK_V_AUDIO = 0x1 << 10,
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CLK_V_APBIF = 0x1 << 11,
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CLK_V_DAM0 = 0x1 << 12,
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CLK_V_DAM1 = 0x1 << 13,
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CLK_V_DAM2 = 0x1 << 14,
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CLK_V_HDA2CODEC_2X = 0x1 << 15,
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CLK_V_ATOMICS = 0x1 << 16,
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CLK_V_ACTMON = 0x1 << 23,
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CLK_V_EXTPERIPH1 = 0x1 << 24,
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CLK_V_SATA = 0x1 << 28,
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CLK_V_HDA = 0x1 << 29,
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CLK_W_HDA2HDMICODEC = 0x1 << 0,
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CLK_W_SATACOLD = 0x1 << 1,
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CLK_W_CEC = 0x1 << 8,
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CLK_W_XUSB_PADCTL = 0x1 << 14,
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CLK_W_ENTROPY = 0x1 << 21,
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CLK_W_AMX0 = 0x1 << 25,
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CLK_W_ADX0 = 0x1 << 26,
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CLK_W_DVFS = 0x1 << 27,
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CLK_W_XUSB_SS = 0x1 << 28,
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CLK_W_MC1 = 0x1 << 30,
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CLK_W_EMC1 = 0x1 << 31,
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CLK_X_AFC0 = 0x1 << 31,
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CLK_X_AFC1 = 0x1 << 30,
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CLK_X_AFC2 = 0x1 << 29,
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CLK_X_AFC3 = 0x1 << 28,
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CLK_X_AFC4 = 0x1 << 27,
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CLK_X_AFC5 = 0x1 << 26,
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CLK_X_AMX1 = 0x1 << 25,
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CLK_X_GPU = 0x1 << 24,
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CLK_X_SOR0 = 0x1 << 22,
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CLK_X_DPAUX = 0x1 << 21,
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CLK_X_ADX1 = 0x1 << 20,
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CLK_X_VIC = 0x1 << 18,
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CLK_X_CLK72MHZ = 0x1 << 17,
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CLK_X_HDMI_AUDIO = 0x1 << 16,
|
||||
CLK_X_EMC_DLL = 0x1 << 14,
|
||||
CLK_X_VIM2_CLK = 0x1 << 11,
|
||||
CLK_X_I2C6 = 0x1 << 6,
|
||||
CLK_X_CAM_MCLK2 = 0x1 << 5,
|
||||
CLK_X_CAM_MCLK = 0x1 << 4,
|
||||
CLK_X_SPARE = 0x1 << 0,
|
||||
};
|
||||
|
||||
/* PLL stabilization delay in usec */
|
||||
#define CLOCK_PLL_STABLE_DELAY_US 300
|
||||
|
||||
#define IO_STABILIZATION_DELAY (2)
|
||||
/* Calculate clock fractional divider value from ref and target frequencies.
|
||||
* This is for a U7.1 format. This is not well written up in the book and
|
||||
* there have been some questions about this macro, so here we go.
|
||||
* U7.1 format is defined as (ddddddd+1) + (h*.5)
|
||||
* The lowest order bit is actually a fractional bit.
|
||||
* Hence, the divider can be thought of as 9 bits.
|
||||
* So:
|
||||
* divider = ((ref/freq) << 1 - 1) (upper 7 bits) |
|
||||
* (ref/freq & 1) (low order half-bit)
|
||||
* however we can't do fractional arithmetic ... these are integers!
|
||||
* So we normalize by shifting the result left 1 bit, and extracting
|
||||
* ddddddd and h directly to the returned u8.
|
||||
* divider = 2*(ref/freq);
|
||||
* We want to
|
||||
* preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as
|
||||
* subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely
|
||||
* situated in the upper 7 bits, and the h is sitting there in the low order
|
||||
* bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number
|
||||
* and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
|
||||
* will assign this to a u8, it gets nicely truncated for you.
|
||||
*/
|
||||
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2)
|
||||
|
||||
/* Calculate clock frequency value from reference and clock divider value
|
||||
* The discussion in the book is pretty lacking.
|
||||
* The idea is that we need to divide a ref clock by a divisor
|
||||
* in U7.1 format, where 7 upper bits are the integer
|
||||
* and lowest order bit is a fraction.
|
||||
* from the book, U7.1 is (ddddddd+1) + (h*.5)
|
||||
* To normalize to an actual number, we might do this:
|
||||
* ((d>>7+1)&0x7f) + (d&1 >> 1)
|
||||
* but as you might guess, the low order bit would be lost.
|
||||
* Since we can't express the fractional bit, we need to multiply it all by 2.
|
||||
* ((d + 2)&0xfe) + (d & 1)
|
||||
* Since we're just adding +2, the lowest order bit is preserved. Hence
|
||||
* (d+2) is the same as ((d + 2)&0xfe) + (d & 1)
|
||||
*
|
||||
* Since you multiply denominator * 2 (by NOT shifting it),
|
||||
* you multiply numerator * 2 to cancel it out.
|
||||
*/
|
||||
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2))
|
||||
|
||||
#define clock_configure_irregular_source(device, src, freq, src_id) \
|
||||
clrsetbits_le32(&clk_rst->clk_src_##device, \
|
||||
CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \
|
||||
src_id << CLK_SOURCE_SHIFT | \
|
||||
CLK_DIVIDER(TEGRA_##src##_KHZ, freq))
|
||||
|
||||
/* Warning: Some devices just use different bits for the same sources for no
|
||||
* apparent reason. *Always* double-check the TRM before trusting this macro. */
|
||||
#define clock_configure_source(device, src, freq) \
|
||||
clock_configure_irregular_source(device, src, freq, src)
|
||||
|
||||
/* The I2C divisors are not 7.1 divisors like the others, they divide by n + 1
|
||||
* directly. Also, there are internal divisors in the I2C controller itself.
|
||||
* We can deal with those here and make it easier to select what the actual
|
||||
* bus frequency will be. The 0x19 value is the default divisor in the
|
||||
* clk_divisor register in the controller, and 8 is just a magic number in the
|
||||
* documentation. Multiplying by 2 compensates for the different format of the
|
||||
* divisor.
|
||||
*/
|
||||
#define clock_configure_i2c_scl_freq(device, src, freq) \
|
||||
clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2)
|
||||
|
||||
enum clock_source { /* Careful: Not true for all sources, always check TRM! */
|
||||
PLLP = 0,
|
||||
PLLC2 = 1,
|
||||
PLLC = 2,
|
||||
PLLD = 2,
|
||||
PLLC3 = 3,
|
||||
PLLA = 3,
|
||||
PLLM = 4,
|
||||
PLLD2 = 5,
|
||||
CLK_M = 6,
|
||||
};
|
||||
|
||||
/* soc-specific */
|
||||
#define TEGRA_CLK_M_KHZ clock_get_osc_khz()
|
||||
#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ
|
||||
#define TEGRA_PLLP_KHZ (408000)
|
||||
#define TEGRA_PLLC_KHZ (600000)
|
||||
#define TEGRA_PLLD_KHZ (925000)
|
||||
#define TEGRA_PLLU_KHZ (960000)
|
||||
|
||||
int clock_get_osc_khz(void);
|
||||
void clock_early_uart(void);
|
||||
void clock_external_output(int clk_id);
|
||||
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
|
||||
u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,
|
||||
u32 same_freq);
|
||||
void clock_cpu0_config_and_reset(void * entry);
|
||||
void clock_halt_avp(void);
|
||||
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
|
||||
void clock_init(void);
|
||||
void clock_init_arm_generic_timer(void);
|
||||
void sor_clock_stop(void);
|
||||
void sor_clock_start(void);
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */
|
||||
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__
|
||||
#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__
|
||||
|
||||
/* ardisplay.h */
|
||||
#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42
|
||||
#define DC_COM_CRC_CONTROL_0 0x300
|
||||
#define DC_COM_CRC_CHECKSUM_0 0x301
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305
|
||||
#define DC_CMD_STATE_ACCESS_0 0x40
|
||||
#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e
|
||||
#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405
|
||||
#define DC_DISP_REF_TO_SYNC_0 0x406
|
||||
#define DC_DISP_SYNC_WIDTH_0 0x407
|
||||
#define DC_DISP_BACK_PORCH_0 0x408
|
||||
#define DC_DISP_DISP_ACTIVE_0 0x409
|
||||
#define DC_DISP_FRONT_PORCH_0 0x40a
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0 0x402
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT)
|
||||
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400
|
||||
#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4
|
||||
#define DC_CMD_DISPLAY_COMMAND_0 0x32
|
||||
#define DC_CMD_STATE_CONTROL_0 0x41
|
||||
#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36
|
||||
|
||||
/* ardisplay_a.h */
|
||||
#define DC_WIN_A_WIN_OPTIONS_0 0x700
|
||||
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30
|
||||
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT)
|
||||
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1)
|
||||
#define DC_WIN_A_BYTE_SWAP_0 0x701
|
||||
#define DC_WIN_A_BUFFER_CONTROL_0 0x702
|
||||
#define DC_WIN_A_COLOR_DEPTH_0 0x703
|
||||
#define DC_WIN_A_POSITION_0 0x704
|
||||
#define DC_WIN_A_SIZE_0 0x705
|
||||
#define DC_WIN_A_PRESCALED_SIZE_0 0x706
|
||||
#define DC_WIN_A_H_INITIAL_DDA_0 0x707
|
||||
#define DC_WIN_A_V_INITIAL_DDA_0 0x708
|
||||
#define DC_WIN_A_DDA_INCREMENT_0 0x709
|
||||
#define DC_WIN_A_LINE_STRIDE_0 0x70a
|
||||
#define DC_WIN_A_DV_CONTROL_0 0x70e
|
||||
#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716
|
||||
#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717
|
||||
#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718
|
||||
#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719
|
||||
#define DC_WINBUF_A_START_ADDR_LO_0 0x800
|
||||
#define DC_WINBUF_A_START_ADDR_HI_0 0x80d
|
||||
#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806
|
||||
#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808
|
||||
|
||||
/* ardisplay_bd.h */
|
||||
#define DC_B_WIN_BD_SIZE_0 0xd85
|
||||
#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86
|
||||
#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a
|
||||
#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83
|
||||
#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0
|
||||
#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1)
|
||||
|
||||
/* arsor.h */
|
||||
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0 0x17
|
||||
#define SOR_NV_PDISP_SOR_PLL1_0 0x18
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0 0x19
|
||||
#define SOR_NV_PDISP_SOR_PLL3_0 0x1a
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e
|
||||
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52
|
||||
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_LVDS_0 0x1c
|
||||
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c
|
||||
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21
|
||||
#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d
|
||||
#define SOR_NV_PDISP_HEAD_STATE1_0 0x7
|
||||
#define SOR_NV_PDISP_HEAD_STATE2_0 0x9
|
||||
#define SOR_NV_PDISP_HEAD_STATE3_0 0xb
|
||||
#define SOR_NV_PDISP_HEAD_STATE4_0 0xd
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0 0x4
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11
|
||||
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64
|
||||
#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60
|
||||
#define SOR_NV_PDISP_SOR_PWR_0 0x15
|
||||
#define SOR_NV_PDISP_SOR_STATE0_0 0x3
|
||||
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2
|
||||
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1
|
||||
|
||||
/* ardpaux.h */
|
||||
#define DPAUX_DP_AUXDATA_READ_W0 0x19
|
||||
|
||||
#define DP_LVDS_SHIFT 25
|
||||
#define DP_LVDS (1 << DP_LVDS_SHIFT)
|
||||
|
||||
#define SRC_BPP 16
|
||||
#define COLORDEPTH 0x6
|
||||
#define COLOR_WHITE 0xFFFFFF
|
||||
|
||||
struct soc_nvidia_tegra132_config; /* forward declaration */
|
||||
void setup_display(struct soc_nvidia_tegra132_config *config);
|
||||
void init_dca_regs(void);
|
||||
void dp_io_powerup(void);
|
||||
u32 dp_setup_timing(u32 width, u32 height);
|
||||
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
|
||||
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
|
||||
u32 pclkfreq, u32 linkfreq);
|
||||
|
||||
#define FB_SIZE_MB (32)
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <timer.h>
|
||||
#include <delay.h>
|
||||
#include <thread.h>
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
}
|
||||
|
||||
void udelay(unsigned usec)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue