purism/librem_skl: add libgfxinit support
Panel settings taken from KBL FSP sample vbt.bin Test: build/boot librem13v2/15v3 with libgfxinit init, verify both LFB and text modes functional Change-Id: I9582065603417e53704244e95dde51a59f709664 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -8,6 +8,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_SKYLAKE
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select SPD_READ_BY_WORD
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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if BOARD_PURISM_BASEBOARD_LIBREM_SKL
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@ -15,3 +15,5 @@
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,28 @@
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--
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-- This file is part of the coreboot project.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(Internal,
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HDMI1,
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others => Disabled);
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end GMA.Mainboard;
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@ -1,5 +1,13 @@
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chip soc/intel/skylake
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register "gpu_pp_up_delay_ms" = "200"
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register "gpu_pp_down_delay_ms" = " 50"
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register "gpu_pp_cycle_delay_ms" = "500"
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register "gpu_pp_backlight_on_delay_ms" = " 1"
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register "gpu_pp_backlight_off_delay_ms" = "200"
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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@ -1,5 +1,13 @@
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chip soc/intel/skylake
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register "gpu_pp_up_delay_ms" = "200"
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register "gpu_pp_down_delay_ms" = " 50"
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register "gpu_pp_cycle_delay_ms" = "500"
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register "gpu_pp_backlight_on_delay_ms" = " 1"
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register "gpu_pp_backlight_off_delay_ms" = "200"
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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