mb/google/mancomb: Add new mainboard
Mancomb is a new Google mainboard with an AMD Cezanne SOC. BUG=b:175143925 TEST=builds Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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# SPDX-License-Identifier: GPL-2.0-or-later
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config BOARD_GOOGLE_BASEBOARD_MANCOMB
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def_bool n
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if BOARD_GOOGLE_BASEBOARD_MANCOMB
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select SOC_AMD_CEZANNE
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config FMDFILE
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string
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
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config MAINBOARD_DIR
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string
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default "google/mancomb"
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config MAINBOARD_PART_NUMBER
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string
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default "Mancomb" if BOARD_GOOGLE_MANCOMB
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config AMD_FWM_POSITION_INDEX
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int
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default 3
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help
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TODO: might need to be adapted for better placement of files in cbfs
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config MAINBOARD_FAMILY
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string
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default "Google_Mancomb"
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endif # BOARD_GOOGLE_BASEBOARD_MANCOMB
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comment "Mancomb"
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config BOARD_GOOGLE_MANCOMB
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bool "-> Mancomb"
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select BOARD_GOOGLE_BASEBOARD_MANCOMB
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# SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += bootblock.c
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ramstage-y += mainboard.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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Vendor name: Google
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Board name: Mancomb
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Category: desktop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <baseboard/variants.h>
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void bootblock_mainboard_early_init(void)
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{
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/* TODO: Perform mainboard initialization */
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}
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FLASH@0xFF000000 16M {
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SI_BIOS {
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RW_MRC_CACHE(PRESERVE) 64K
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RW_SECTION_A 3M {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 256
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}
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RW_SECTION_B 3M {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 256
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}
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 20K
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SMMSTORE(PRESERVE) 4K
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RW_LEGACY(CBFS)
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WP_RO@8M 8M {
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 448K
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COREBOOT(CBFS)
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}
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}
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock (
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/device.h>
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static void mainboard_init(void *chip_info)
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{
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/* TODO: Perform mainboard initialization */
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}
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static void mainboard_enable(struct device *dev)
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{
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/* TODO: Enable mainboard */
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/amd/cezanne
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device domain 0 on
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end # domain
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end # chip soc/amd/cezanne
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#endif /* __BASEBOARD_GPIO_H__ */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#endif /* __BASEBOARD_VARIANTS_H__ */
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