mb/google/mancomb: Add new mainboard

Mancomb is a new Google mainboard with an AMD Cezanne SOC.

BUG=b:175143925
TEST=builds

Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mathew King 2020-12-08 11:33:58 -07:00 committed by Patrick Georgi
parent e75f1807e1
commit 422501fb14
11 changed files with 151 additions and 0 deletions

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# SPDX-License-Identifier: GPL-2.0-or-later
config BOARD_GOOGLE_BASEBOARD_MANCOMB
def_bool n
if BOARD_GOOGLE_BASEBOARD_MANCOMB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select SOC_AMD_CEZANNE
config FMDFILE
string
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
config MAINBOARD_DIR
string
default "google/mancomb"
config MAINBOARD_PART_NUMBER
string
default "Mancomb" if BOARD_GOOGLE_MANCOMB
config AMD_FWM_POSITION_INDEX
int
default 3
help
TODO: might need to be adapted for better placement of files in cbfs
config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
config MAINBOARD_FAMILY
string
default "Google_Mancomb"
endif # BOARD_GOOGLE_BASEBOARD_MANCOMB

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comment "Mancomb"
config BOARD_GOOGLE_MANCOMB
bool "-> Mancomb"
select BOARD_GOOGLE_BASEBOARD_MANCOMB

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# SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += bootblock.c
ramstage-y += mainboard.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

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Vendor name: Google
Board name: Mancomb
Category: desktop
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <baseboard/variants.h>
void bootblock_mainboard_early_init(void)
{
/* TODO: Perform mainboard initialization */
}

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FLASH@0xFF000000 16M {
SI_BIOS {
RW_MRC_CACHE(PRESERVE) 64K
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 4K
RW_LEGACY(CBFS)
WP_RO@8M 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
}
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock (
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001 /* OEM Revision */
)
{
#include <acpi/dsdt_top.asl>
#include <soc.asl>
}

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/device.h>
static void mainboard_init(void *chip_info)
{
/* TODO: Perform mainboard initialization */
}
static void mainboard_enable(struct device *dev)
{
/* TODO: Enable mainboard */
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne
device domain 0 on
end # domain
end # chip soc/amd/cezanne

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
#endif /* __BASEBOARD_GPIO_H__ */

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
#endif /* __BASEBOARD_VARIANTS_H__ */