soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTF

This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL
platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/intel/apollolake/Kconfig

@@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_GPIO_LIB
 	select HAVE_ASAN_IN_ROMSTAGE
 	select HAVE_CF9_RESET_PREPARE
+	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE

src/soc/intel/cannonlake/Kconfig

@@ -65,6 +65,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
+	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_HYPERTHREADING

src/soc/intel/jasperlake/Kconfig

@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
+	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER