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mb/google/hatch/akemi: disable unused devices for Akemi 

Akemi unused devices declare:
     - I2C #1 gpio_keys
     - close I2C #3
     - close GSPO #1

BUG=b:142800988
TEST=Reboot stress test and suspend stress test, the DUT will be
able to working properly

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2019-10-17 08:28:42 +08:00 committed by Patrick Georgi
parent fedf71c6fb
commit 422807387b
1 changed files with 5 additions and 61 deletions
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66
src/mainboard/google/hatch/variants/akemi/overridetree.cb
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@ -3,10 +3,10 @@ chip soc/intel/cannonlake
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
@ -43,11 +43,6 @@ chip soc/intel/cannonlake
.rise_time_ns = 60, .rise_time_ns = 60,
.fall_time_ns = 25, .fall_time_ns = 25,
}, },
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 150,
.fall_time_ns = 150,
},
.i2c[4] = { .i2c[4] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 120, .rise_time_ns = 120,
@ -108,51 +103,9 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end device i2c 5d on end
end end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
register "key.wake" = "GPE0_DW0_08"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end # I2C #1 end # I2C #1
device pci 15.2 off end # I2C #2 device pci 15.2 off end # I2C #2
device pci 15.3 on device pci 15.3 off end # I2C #3
chip drivers/i2c/sx9310
register "desc" = ""SAR Proximity Sensor""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "1"
register "reg_prox_ctrl0" = "0x10"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
register "reg_prox_ctrl7" = "0x0d"
register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x1f"
register "reg_prox_ctrl11" = "0x00"
register "reg_prox_ctrl12" = "0x00"
register "reg_prox_ctrl13" = "0x00"
register "reg_prox_ctrl14" = "0x00"
register "reg_prox_ctrl15" = "0x00"
register "reg_prox_ctrl16" = "0x00"
register "reg_prox_ctrl17" = "0x00"
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
register "reg_sar_ctrl1" = "0x8a"
register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C #3
device pci 19.0 on device pci 19.0 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
@ -168,16 +121,7 @@ chip soc/intel/cannonlake
end end
end #I2C #4 end #I2C #4
device pci 1a.0 on end # eMMC device pci 1a.0 on end # eMMC
device pci 1e.3 on device pci 1e.3 off end # GSPI #1
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
device spi 1 on end
end # FPMCU
end # GSPI #1
end end
end end