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mb/asus/p5gc-mx: Implement resume from S3 support 

Needs the ramstage configuration enabling of SuperIO GPIO pnp devices
for BSEL straps.

Also needs VSBGATE# to be on for ram to be powered during S3.

TESTED with 800MHz and 1067MHz FSB CPUs at the correct straps when
resuming from S3.

Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2017-05-06 00:28:12 +02:00 committed by Martin Roth
parent 1440c66b16
commit 42315688b5
3 changed files with 25 additions and 16 deletions
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1
src/mainboard/asus/p5gc-mx/Kconfig
View File

@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE

13
src/mainboard/asus/p5gc-mx/devicetree.cb
View File

@ -113,9 +113,20 @@ chip northbridge/intel/i945
device pnp 2e.6 off end # SPI
device pnp 2e.7 on end # GPIO6
device pnp 2e.8 off end # WDTO# & PLED
device pnp 2e.9 on end # GPIO2-5
device pnp 2e.9 off end # GPIO2
device pnp 2e.109 on # GPIO3
irq 0xf0 = 0xf3 # BSEL straps to output
irq 0xf2 = 0x08 # INVERT GPIO33
end
device pnp 2e.209 on # GPIO4
irq 0xf5 = 0xf8
end
device pnp 2e.309 on # GPIO5
irq 0xe0 = 0xde
end
device pnp 2e.a on # ACPI
irq 0x70 = 0
irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
end
device pnp 2e.b on # HWM
io 0x60 = 0x290

27
src/mainboard/asus/p5gc-mx/romstage.c
View File

@ -49,7 +49,7 @@
* BSEL1 is connected with GPIO33 with inversed logic
* BSEL2 is connected with GPIO55
*/
static void setup_sio_gpio(u8 bsel)
static int setup_sio_gpio(u8 bsel)
{
int need_reset = 0;
u8 reg, old_reg;
@ -83,13 +83,7 @@ static void setup_sio_gpio(u8 bsel)
pnp_exit_ext_func_mode(GPIO_DEV);
if (need_reset) {
int i = 1000;
while (i--)
outb(i & 0xff, 0x80);
outb(0xe, 0xcf9);
halt();
}
return need_reset;
}
static u8 msr_get_fsb(void)
@ -197,7 +191,6 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
u8 m_bsel;
u8 c_bsel = msr_get_fsb();
timestamp_init(get_initial_timestamp());
@ -210,8 +203,6 @@ void mainboard_romstage_entry(unsigned long bist)
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_sio_gpio(c_bsel);
/* Set up the console */
console_init();
@ -228,11 +219,19 @@ void mainboard_romstage_entry(unsigned long bist)
*/
i945_early_initialization();
m_bsel = MCHBAR32(CLKCFG) & 7;
printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel);
s3resume = southbridge_detect_s3_resume();
/*
* Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
* Some CPU accept this others don't.
*/
if (!s3resume && setup_sio_gpio(c_bsel)) {
printk(BIOS_DEBUG,
"Needs reset to configure CPU BSEL straps\n");
outb(0xe, 0xcf9);
halt();
}
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();