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riscv: Use the generic src/lib/bootblock.c 

TEST=Compiled for and ran on spike; it booted as before.

Change-Id: Id173643a3571962406f9191db248b206235dca35
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Jonathan Neuschäfer 2016-10-12 00:18:01 +02:00 committed by Ronald G. Minnich
parent bebeb7497d
commit 4247426be6
5 changed files with 0 additions and 64 deletions
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1
src/arch/riscv/Kconfig
View File

@ -6,7 +6,6 @@ config ARCH_BOOTBLOCK_RISCV
bool
default n
select ARCH_RISCV
select BOOTBLOCK_CUSTOM
select C_ENVIRONMENT_BOOTBLOCK
config ARCH_VERSTAGE_RISCV

1
src/mainboard/emulation/qemu-riscv/Makefile.inc
View File

@ -12,7 +12,6 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
bootblock-y += bootblock.c
bootblock-y += uart.c
bootblock-y += qemu_util.c
bootblock-y += rom_media.c

31
src/mainboard/emulation/qemu-riscv/bootblock.c
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/exception.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <program_loading.h>
// the qemu part of all this is very, very non-hardware like.
// so it gets its own bootblock.
void main(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
}
run_romstage();
}

1
src/mainboard/emulation/spike-riscv/Makefile.inc
View File

@ -12,7 +12,6 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
bootblock-y += bootblock.c
bootblock-y += uart.c
bootblock-y += spike_util.c
bootblock-y += rom_media.c

30
src/mainboard/emulation/spike-riscv/bootblock.c
View File

@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/exception.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <program_loading.h>
// the qemu part of all this is very, very non-hardware like.
// so it gets its own bootblock.
void main(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
}
run_romstage();
}