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mb/google/dedede/var/lantis: Update DPTF parameters 

DPTF paramerters from thermal team.

1. PL2 =15W
2. Add TSR sensor charger, 5V regulator

BUG=b:177249297
BRANCH=dedede
TEST=build image and verified by thermal team.

Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Tony Huang 2021-03-12 15:06:29 +08:00 committed by Patrick Georgi
parent efe873e633
commit 4248d8e7bb
1 changed files with 23 additions and 8 deletions
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31
src/mainboard/google/dedede/variants/lantis/overridetree.cb
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@ -62,7 +62,7 @@ chip soc/intel/jasperlake
register "power_limits_config" = "{ register "power_limits_config" = "{
.tdp_pl1_override = 6, .tdp_pl1_override = 6,
.tdp_pl2_override = 20, .tdp_pl2_override = 15,
}" }"
device domain 0 on device domain 0 on
@ -70,18 +70,24 @@ chip soc/intel/jasperlake
chip drivers/intel/dptf chip drivers/intel/dptf
register "options.tsr[0].desc" = ""Memory"" register "options.tsr[0].desc" = ""Memory""
register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""5V regulator""
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)
}" }"
## Critical Policy ## Critical Policy
register "policies.critical" = "{ register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 105, SHUTDOWN)
}" }"
## Power Limits Control ## Power Limits Control
register "controls.power_limits" = "{ register "controls.power_limits" = "{
@ -93,13 +99,22 @@ chip soc/intel/jasperlake
.granularity = 200, .granularity = 200,
}, },
.pl2 = { .pl2 = {
.min_power = 20000, .min_power = 15000,
.max_power = 20000, .max_power = 15000,
.time_window_min = 1 * MSECS_PER_SEC, .time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000, .granularity = 1000,
} }
}" }"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 0 on end device generic 0 on end
end end
end # SA Thermal device end # SA Thermal device