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soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init 

Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.

BUG=None
TEST=Build and boot to OS in Guybrush.

Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-09-20 16:31:33 +02:00 committed by Felix Held
parent ef90f07d06
commit 425e73d3f5
3 changed files with 9 additions and 3 deletions
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4
src/soc/amd/cezanne/early_fch.c
View File

@ -44,9 +44,11 @@ void configure_port80_routing_early(void)
/* Before console init */ /* Before console init */
void fch_pre_init(void) void fch_pre_init(void)
{ {
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
lpc_early_init(); lpc_early_init();
fch_spi_early_init(); fch_spi_early_init();
enable_acpimmio_decode_pm04();
fch_smbus_init(); fch_smbus_init();
fch_enable_cf9_io(); fch_enable_cf9_io();
fch_enable_legacy_io(); fch_enable_legacy_io();

4
src/soc/amd/picasso/early_fch.c
View File

@ -42,13 +42,15 @@ static void reset_i2c_peripherals(void)
/* Before console init */ /* Before console init */
void fch_pre_init(void) void fch_pre_init(void)
{ {
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
lpc_early_init(); lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes(); lpc_configure_decodes();
fch_spi_early_init(); fch_spi_early_init();
enable_acpimmio_decode_pm04();
fch_smbus_init(); fch_smbus_init();
fch_enable_cf9_io(); fch_enable_cf9_io();
fch_enable_legacy_io(); fch_enable_legacy_io();

4
src/soc/amd/stoneyridge/southbridge.c
View File

@ -328,6 +328,9 @@ void bootblock_fch_early_init(void)
{ {
int reboot = 0; int reboot = 0;
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
lpc_enable_rom(); lpc_enable_rom();
sb_enable_lpc(); sb_enable_lpc();
lpc_enable_port80(); lpc_enable_port80();
@ -335,7 +338,6 @@ void bootblock_fch_early_init(void)
lpc_enable_spi_prefetch(); lpc_enable_spi_prefetch();
sb_init_spi_base(); sb_init_spi_base();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
enable_acpimmio_decode_pm04();
fch_smbus_init(); fch_smbus_init();
fch_enable_cf9_io(); fch_enable_cf9_io();
setup_spread_spectrum(&reboot); setup_spread_spectrum(&reboot);