soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -44,9 +44,11 @@ void configure_port80_routing_early(void)
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/* Before console init */
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void fch_pre_init(void)
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{
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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lpc_early_init();
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fch_spi_early_init();
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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fch_enable_cf9_io();
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fch_enable_legacy_io();
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@ -42,13 +42,15 @@ static void reset_i2c_peripherals(void)
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/* Before console init */
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void fch_pre_init(void)
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{
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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lpc_early_init();
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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lpc_configure_decodes();
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fch_spi_early_init();
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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fch_enable_cf9_io();
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fch_enable_legacy_io();
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@ -328,6 +328,9 @@ void bootblock_fch_early_init(void)
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{
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int reboot = 0;
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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lpc_enable_rom();
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sb_enable_lpc();
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lpc_enable_port80();
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@ -335,7 +338,6 @@ void bootblock_fch_early_init(void)
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lpc_enable_spi_prefetch();
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sb_init_spi_base();
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sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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fch_enable_cf9_io();
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setup_spread_spectrum(&reboot);
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