sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB

Use common code to detect ACPI S3.

Tested on Thinkpad X60.

Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/apple/macbook21/romstage.c

@@ -29,6 +29,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 
 static void ich7_enable_lpc(void)
 {

src/mainboard/asrock/g41c-gs/romstage.c

@@ -23,6 +23,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6776/nct6776.h>

src/mainboard/asus/p5gc-mx/romstage.c

@@ -32,6 +32,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
 #include <arch/cpu.h>

src/mainboard/asus/p5qpl-am/romstage.c

@@ -27,6 +27,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>

src/mainboard/foxconn/g41s-k/romstage.c

@@ -22,6 +22,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8720f/it8720f.h>

src/mainboard/getac/p470/romstage.c

@@ -28,6 +28,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 #include "option_table.h"
 
 static void setup_special_ich7_gpios(void)

src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c

@@ -28,6 +28,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)

src/mainboard/gigabyte/ga-g41m-es2l/romstage.c

@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>

src/mainboard/ibase/mb899/romstage.c

@@ -31,6 +31,7 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <southbridge/intel/common/pmclib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)

src/mainboard/intel/d945gclf/romstage.c

@@ -26,6 +26,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
 #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)

src/mainboard/intel/dg41wv/romstage.c

@@ -23,6 +23,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>

src/mainboard/kontron/986lcd-m/romstage.c

@@ -30,6 +30,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 

src/mainboard/lenovo/t60/romstage.c

@@ -32,6 +32,7 @@
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include "dock.h"
 
 static void ich7_enable_lpc(void)

src/mainboard/lenovo/thinkcentre_a58/romstage.c

@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>

src/mainboard/lenovo/x60/romstage.c

@@ -33,6 +33,7 @@
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include "dock.h"
 
 static void ich7_enable_lpc(void)

src/mainboard/lenovo/z61t/romstage.c

@@ -33,6 +33,7 @@
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include "dock.h"
 
 static void ich7_enable_lpc(void)

src/mainboard/roda/rk886ex/romstage.c

@@ -30,6 +30,7 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
 #include "option_table.h"
 
 static void ich7_enable_lpc(void)

src/northbridge/intel/pineview/romstage.c

@@ -26,6 +26,7 @@
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>

src/southbridge/intel/i82801gx/Kconfig

@@ -25,6 +25,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
+	select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select INTEL_HAS_TOP_SWAP

src/southbridge/intel/i82801gx/Makefile.inc

@@ -34,6 +34,6 @@ ramstage-y += watchdog.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
-romstage-y += early_smbus.c early_lpc.c
+romstage-y += early_smbus.c
 
 endif

src/southbridge/intel/i82801gx/early_lpc.c

@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include "i82801gx.h"
-
-int southbridge_detect_s3_resume(void)
-{
-	u32 reg32;
-
-	/* Read PM1_CNT */
-	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-	if (((reg32 >> 10) & 7) == 5) {
-		if (!acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-			return 1;
-		}
-	}
-
-	return 0;
-}

src/southbridge/intel/i82801gx/i82801gx.h

@@ -48,7 +48,6 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
 int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
 		const u8 *buf);
-int southbridge_detect_s3_resume(void);
 #endif
 #endif