- Update to a working version for the hdama board
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
e058a1e418
commit
4264415c6e
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@ -7,6 +7,111 @@
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#warning "FIXME move these delay functions somewhere more appropriate"
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#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz"
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static void print_clock_multiplier(void)
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{
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msr_t msr;
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print_debug("clock multipler: 0x");
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msr = rdmsr(0xc0010042);
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print_debug_hex32(msr.lo & 0x3f);
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print_debug(" = 0x");
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print_debug_hex32(((msr.lo & 0x3f) + 8) * 100);
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print_debug("Mhz\r\n");
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}
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static unsigned usecs_to_ticks(unsigned usecs)
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{
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#warning "FIXME make usecs_to_ticks work properly"
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#if 1
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return usecs *2000;
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#else
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/* This can only be done if cpuid says fid changing is supported
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* I need to look up the base frequency another way for other
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* cpus. Is it worth dedicating a global register to this?
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* Are the PET timers useable for this purpose?
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*/
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msr_t msr;
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msr = rdmsr(0xc0010042);
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return ((msr.lo & 0x3f) + 8) * 100 *usecs;
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#endif
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}
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static void init_apic_timer(void)
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{
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, end;
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/* Set the apic timer to no interrupts and periodic mode */
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apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0);
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/* Set the divider to 1, no divider */
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apic_reg[0x3e0 >> 2] = (1 << 3) | 3;
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/* Set the initial counter to 0xffffffff */
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apic_reg[0x380 >> 2] = 0xffffffff;
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}
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static void udelay(unsigned usecs)
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{
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#if 1
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uint32_t start, ticks;
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tsc_t tsc;
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/* Calculate the number of ticks to run for */
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ticks = usecs_to_ticks(usecs);
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/* Find the current time */
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tsc = rdtsc();
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start = tsc.lo;
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do {
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tsc = rdtsc();
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} while((tsc.lo - start) < ticks);
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#else
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, value, ticks;
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/* Calculate the number of ticks to run for */
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ticks = usecs * 200;
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start = apic_reg[0x390 >> 2];
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do {
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value = apic_reg[0x390 >> 2];
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} while((start - value) < ticks);
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#endif
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}
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static void mdelay(unsigned msecs)
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{
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int i;
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for(i = 0; i < msecs; i++) {
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udelay(1000);
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}
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}
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static void delay(unsigned secs)
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{
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int i;
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for(i = 0; i < secs; i++) {
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mdelay(1000);
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}
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}
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static void memreset_setup(const struct mem_controller *ctrl)
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{
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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print_debug("memreset lo\r\n");
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}
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static void memreset(const struct mem_controller *ctrl)
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{
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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print_debug("memreset hi\r\n");
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udelay(50);
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}
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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@ -27,9 +132,7 @@ static int boot_cpu(void)
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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if (bsp) {
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print_debug("Bootstrap processor\r\n");
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} else {
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print_debug("Application processor\r\n");
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print_debug("Bootstrap cpu\r\n");
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}
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return bsp;
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@ -116,24 +219,71 @@ static void dump_pci_device(unsigned dev)
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}
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}
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static void dump_spd_registers(void)
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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unsigned device;
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device = SMBUS_MEM_DEVICE_START;
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print_debug("\r\n");
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while(device <= SMBUS_MEM_DEVICE_END) {
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(i = 0; i < 256; i++) {
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((i & 0xf) == 0) {
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(i);
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, i);
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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@ -142,41 +292,148 @@ static void dump_spd_registers(void)
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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device += SMBUS_MEM_DEVICE_INC;
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print_debug("\r\n");
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}
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}
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}
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static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg)
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{
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outb(reg, port);
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outb(value, port +1);
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}
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static unsigned char pnp_read_config(unsigned char port, unsigned char reg)
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{
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outb(reg, port);
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return inb(port +1);
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}
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static void pnp_set_logical_device(unsigned char port, int device)
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{
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pnp_write_config(port, device, 0x07);
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}
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static void pnp_set_enable(unsigned char port, int enable)
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{
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pnp_write_config(port, enable?0x1:0x0, 0x30);
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}
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static int pnp_read_enable(unsigned char port)
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{
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return !!pnp_read_config(port, 0x30);
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}
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static void pnp_set_iobase0(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x60);
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pnp_write_config(port, iobase & 0xff, 0x61);
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}
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static void pnp_set_iobase1(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x62);
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pnp_write_config(port, iobase & 0xff, 0x63);
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}
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static void pnp_set_irq0(unsigned char port, unsigned irq)
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{
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pnp_write_config(port, irq, 0x70);
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}
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static void pnp_set_irq1(unsigned char port, unsigned irq)
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{
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pnp_write_config(port, irq, 0x72);
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}
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static void pnp_set_drq(unsigned char port, unsigned drq)
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{
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pnp_write_config(port, drq & 0xff, 0x74);
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}
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#define PC87360_FDC 0x00
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#define PC87360_PP 0x01
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#define PC87360_SP2 0x02
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#define PC87360_SP1 0x03
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#define PC87360_SWC 0x04
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#define PC87360_KBCM 0x05
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#define PC87360_KBCK 0x06
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#define PC87360_GPIO 0x07
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#define PC87360_ACB 0x08
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#define PC87360_FSCM 0x09
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#define PC87360_WDT 0x0A
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static void pc87360_enable_serial(void)
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{
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pnp_set_logical_device(SIO_BASE, PC87360_SP1);
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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static void main(void)
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{
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static const struct mem_controller cpu0 = {
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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.memreset = 28,
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};
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static const struct mem_controller cpu1 = {
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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.memreset = 29,
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};
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pc87360_enable_serial();
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uart_init();
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console_init();
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#if 0
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print_debug(" XIP_ROM_BASE: ");
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print_debug_hex32(XIP_ROM_BASE);
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print_debug(" XIP_ROM_SIZE: ");
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print_debug_hex32(XIP_ROM_SIZE);
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print_debug("\r\n");
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#endif
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if (boot_cpu() && !cpu_init_detected()) {
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#if 1
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init_apic_timer();
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#endif
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain();
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print_pci_devices();
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enable_smbus();
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sdram_initialize();
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dump_spd_registers(&cpu0);
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sdram_initialize(&cpu0);
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dump_spd_registers();
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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/* Check the first 512M */
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/* Check all of memory */
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#if 0
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ram_check(0x00000000, msr.lo);
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#else
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/* Check 16MB of memory */
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ram_check(0x00000000, 0x1600000);
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#endif
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#if 0
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print_debug("sleeping 15s\r\n");
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delay(15);
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print_debug("sleeping 15s done\r\n");
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#endif
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}
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}
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@ -9,129 +9,3 @@ unsigned long initial_apicid[MAX_CPUS] =
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{
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0
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};
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void
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mainboard_fixup(void)
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{
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}
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void
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final_mainboard_fixup(void)
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{
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#if 0
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// void final_southbridge_fixup(void);
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// void final_superio_fixup(void);
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printk_info("AMD Solo initializing...");
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// final_southbridge_fixup();
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//#ifndef USE_NEW_SUPERIO_INTERFACE
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//final_superio_fixup();
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//#endif
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#endif
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}
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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};
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static struct ioapicreg ioapicregvalues[] = {
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#define ALL (0xff << 24)
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#define NONE (0)
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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/* mask, trigger, polarity, destination, delivery, vector */
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{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
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{0x01, DISABLED, NONE},
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{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
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{0x03, DISABLED, NONE},
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{0x04, DISABLED, NONE},
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{0x05, DISABLED, NONE},
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{0x06, DISABLED, NONE},
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{0x07, DISABLED, NONE},
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{0x08, DISABLED, NONE},
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{0x09, DISABLED, NONE},
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{0x0a, DISABLED, NONE},
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{0x0b, DISABLED, NONE},
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{0x0c, DISABLED, NONE},
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{0x0d, DISABLED, NONE},
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{0x0e, DISABLED, NONE},
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{0x0f, DISABLED, NONE},
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{0x10, DISABLED, NONE},
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{0x11, DISABLED, NONE},
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{0x12, DISABLED, NONE},
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{0x13, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x15, DISABLED, NONE},
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{0x16, DISABLED, NONE},
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{0x17, DISABLED, NONE},
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{0x18, DISABLED, NONE},
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{0x19, DISABLED, NONE},
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{0x20, DISABLED, NONE},
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{0x21, DISABLED, NONE},
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{0x22, DISABLED, NONE},
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{0x23, DISABLED, NONE},
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};
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static void setup_ioapic(void)
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{
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int i;
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unsigned long value_low, value_high;
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unsigned long ioapic_base = 0xfec00000;
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volatile unsigned long *l;
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struct ioapicreg *a = ioapicregvalues;
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l = (unsigned long *) ioapic_base;
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for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
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i++, a++) {
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l[0] = (a->reg * 2) + 0x10;
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l[4] = a->value_low;
|
||||
value_low = l[4];
|
||||
l[0] = (a->reg *2) + 0x11;
|
||||
l[4] = a->value_high;
|
||||
value_high = l[4];
|
||||
if ((i==0) && (value_low == 0xffffffff)) {
|
||||
printk_warning("IO APIC not responding.\n");
|
||||
return;
|
||||
}
|
||||
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||
a->reg, a->value_low, a->value_high);
|
||||
}
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
printk_debug("lpc_init\n");
|
||||
#if 0
|
||||
pci_read_config_byte(dev, 0x4B, &byte);
|
||||
byte |= 1;
|
||||
pci_write_config_byte(dev, 0x4B, byte);
|
||||
setup_ioapic();
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x7468,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,8 +8,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LNXI ";
|
||||
static const char productid[12] = "P4DPR ";
|
||||
static const char productid[12] = "HDAMA ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
unsigned char bus_8111_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -30,79 +35,192 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "ISA ");
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 3;
|
||||
bus_isa = 4;
|
||||
}
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n");
|
||||
|
||||
bus_8131_1 = 1;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n");
|
||||
|
||||
bus_8131_2 = 2;
|
||||
}
|
||||
}
|
||||
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
/* 8131 apic 3 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x11, base);
|
||||
}
|
||||
/* 8131 apic 4 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x11, base);
|
||||
}
|
||||
}
|
||||
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, 0x02, 0x00);
|
||||
bus_isa, 0x00, 0x02, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x01, 0x02, 0x01);
|
||||
bus_isa, 0x01, 0x02, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, 0x02, 0x02);
|
||||
bus_isa, 0x00, 0x02, 0x02);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x03, 0x02, 0x03);
|
||||
bus_isa, 0x03, 0x02, 0x03);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x04, 0x02, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x05, 0x02, 0x05);
|
||||
bus_isa, 0x04, 0x02, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x06, 0x02, 0x06);
|
||||
bus_isa, 0x05, 0x02, 0x05);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x07, 0x02, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
0x03, 0x08, 0x02, 0x08);
|
||||
bus_isa, 0x06, 0x02, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x09, 0x02, 0x09);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x0a, 0x02, 0x0a);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x0b, 0x02, 0x0b);
|
||||
bus_isa, 0x07, 0x02, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0c, 0x02, 0x0c);
|
||||
bus_isa, 0x08, 0x02, 0x08);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0d, 0x02, 0x0d);
|
||||
bus_isa, 0x09, 0x02, 0x09);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0e, 0x02, 0x0e);
|
||||
bus_isa, 0x0a, 0x02, 0x0a);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0f, 0x02, 0x0f);
|
||||
bus_isa, 0x0b, 0x02, 0x0b);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0c, 0x02, 0x0c);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0d, 0x02, 0x0d);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0e, 0x02, 0x0e);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0f, 0x02, 0x0f);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, MP_APIC_ALL, 0x00);
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x00, 0x00, MP_APIC_ALL, 0x01);
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
|
||||
/* 8111 DevB.3 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x00, (5<<2)|3, 0x02, 0x13);
|
||||
|
||||
/* AGP Slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x01, (0<<2)|0, 0x02, 0x10);
|
||||
0x03, (6<<2)|0, 0x02, 0x12);
|
||||
|
||||
/* PCI Slot 1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|0, 0x04, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|1, 0x04, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|2, 0x04, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|3, 0x04, 0x10);
|
||||
|
||||
/* PCI Slot 2 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (5 <<2)|0, 0x02, 0x11);
|
||||
bus_8131_2, (2<<2)|0, 0x04, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|1, 0x04, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|2, 0x04, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|3, 0x04, 0x11);
|
||||
|
||||
/* PCI Slot 3 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|0, 0x03, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|1, 0x03, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|2, 0x03, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|3, 0x03, 0x10);
|
||||
|
||||
/* PCI Slot 4 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (7<<2)|0, 0x02, 0x13);
|
||||
|
||||
/* AMR Slot */
|
||||
bus_8131_1, (2<<2)|0, 0x03, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (1<<2)|0, 0x02, 0x10);
|
||||
bus_8131_1, (2<<2)|1, 0x03, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|2, 0x03, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|3, 0x03, 0x11);
|
||||
|
||||
/* PCI Slot 5 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|0, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|1, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|2, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|3, 0x02, 0x10);
|
||||
|
||||
/* PCI Slot 6 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|0, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|1, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|2, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|3, 0x02, 0x13);
|
||||
|
||||
/* On board nics */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (3<<2)|0, 0x03, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (4<<2)|0, 0x03, 0x10);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
|
|
|
|||
Loading…
Reference in New Issue