soc/intel/common: Set controller state to active in GSPI init
Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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@ -23,6 +23,7 @@
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/spi.h>
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#include <intelblocks/spi.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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@ -446,8 +447,19 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus)
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static int gspi_ctrlr_setup(const struct spi_slave *dev)
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static int gspi_ctrlr_setup(const struct spi_slave *dev)
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{
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{
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struct spi_cfg cfg;
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struct spi_cfg cfg;
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int devfn;
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uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
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uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
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struct gspi_ctrlr_params params, *p = ¶ms;
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struct gspi_ctrlr_params params, *p = ¶ms;
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const struct device *device;
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devfn = gspi_soc_bus_to_devfn(dev->bus);
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if (devfn < 0) {
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printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
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__func__, dev->bus);
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return -1;
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}
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device = pcidev_path_on_root(devfn);
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/* Only chip select 0 is supported. */
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/* Only chip select 0 is supported. */
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if (dev->cs != 0) {
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if (dev->cs != 0) {
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@ -466,6 +478,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
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return -1;
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return -1;
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}
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}
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/* Ensure controller is in D0 state */
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lpss_set_power_state(device, STATE_D0);
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/* Take controller out of reset, keeping DMA in reset. */
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/* Take controller out of reset, keeping DMA in reset. */
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gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);
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gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);
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