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soc/intel/common: Set controller state to active in GSPI init 

Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.

BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
     sequence for CML and ICL platforms.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Meera Ravindranath 2019-07-19 15:32:29 +05:30 committed by Subrata Banik
parent 46445155ea
commit 4288cda2ed
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/common/block/gspi/gspi.c
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@ -23,6 +23,7 @@
#include <device/pci_ops.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpss.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@ -446,8 +447,19 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus)
static int gspi_ctrlr_setup(const struct spi_slave *dev)
{
struct spi_cfg cfg;
int devfn;
uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
struct gspi_ctrlr_params params, *p = &params;
const struct device *device;
devfn = gspi_soc_bus_to_devfn(dev->bus);
if (devfn < 0) {
printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
__func__, dev->bus);
return -1;
}
device = pcidev_path_on_root(devfn);
/* Only chip select 0 is supported. */
if (dev->cs != 0) {
@ -466,6 +478,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
return -1;
}
/* Ensure controller is in D0 state */
lpss_set_power_state(device, STATE_D0);
/* Take controller out of reset, keeping DMA in reset. */
gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);