Various cosmetic and coding style fixes in CAR code (trivial).
Also, whitespace fixes, consistency fixes, and drop some of the less useful comments. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
1d36d6df7d
commit
4292684e1a
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@ -18,13 +18,16 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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/* leave some space for global variable to pass to RAM stage */
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/* Leave some space for global variable to pass to RAM stage. */
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#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
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/* for CAR with FAM10 */
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/* For CAR with Fam10h. */
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#define CacheSizeAPStack 0x400 /* 1K */
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#define MSR_MCFG_BASE 0xC0010058
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@ -35,59 +38,62 @@
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#define CPUID_MASK 0x0ff00f00
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#define CPUID_VAL_FAM10_ROTATED 0x0f000010
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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/*
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* XMM map:
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* xmm1: cpu family
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* xmm2: fam10 comparison value
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* xmm3: backup ebx
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* xmm1: CPU family
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* xmm2: Fam10h comparison value
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* xmm3: Backup EBX
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*/
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/* Save the BIST result */
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/* Save the BIST result. */
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movl %eax, %ebp
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/* for normal part %ebx already contain cpu_init_detected from fallback call */
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/*
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* For normal part %ebx already contain cpu_init_detected
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* from fallback call.
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*/
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cache_as_ram_setup:
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post_code(0xa0)
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/* enable SSE */
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/* Enable SSE. */
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movl %cr4, %eax
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orl $(3<<9), %eax
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orl $(3 << 9), %eax
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movl %eax, %cr4
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/* figure out cpu family */
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/* Figure out the CPU family. */
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cvtsi2sd %ebx, %xmm3
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movl $0x01, %eax
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cpuid
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/* base family is bits 8..11, extended family is bits 20..27 */
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/* Base family is bits 8..11, extended family is bits 20..27. */
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andl $CPUID_MASK, %eax
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/* reorder bits for easier comparison by value */
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/* Reorder bits for easier comparison by value. */
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roll $0x10, %eax
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cvtsi2sd %eax, %xmm1
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movl $CPUID_VAL_FAM10_ROTATED, %eax
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cvtsi2sd %eax, %xmm2
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cvtsd2si %xmm3, %ebx
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/* check if cpu_init_detected */
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/* Check if cpu_init_detected. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(1 << 11), %eax
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movl %eax, %ebx /* We store the status */
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movl %eax, %ebx /* We store the status. */
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jmp_if_k8(CAR_FAM10_out_post_errata)
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/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
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/* Only BSP needed, for other nodes set during HT/memory init. */
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/* So we need to check if it is BSP */
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/*
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* For GH, CAR need to set DRAM Base/Limit registers to direct that
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* to node0.
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* Only BSP needed, for other nodes set during HT/memory init.
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* So we need to check if it is BSP.
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*/
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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bt $8, %eax /* BSC */
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jnc CAR_FAM10_out
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/* Enable RT tables on BSP */
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/* Enable RT tables on BSP. */
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movl $0x8000c06c, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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@ -96,7 +102,7 @@ cache_as_ram_setup:
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btr $0, %eax
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outl %eax, %dx
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/* Setup temporary DRAM map: [0,16M) bit 0-23 */
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/* Setup temporary DRAM map: [0,16M) bit 0-23. */
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movl $0x8000c144, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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@ -113,8 +119,9 @@ cache_as_ram_setup:
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CAR_FAM10_out:
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/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
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* Re-enable it in after RAM is initialized and before CAR is disabled
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/*
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* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
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* Re-enable it in after RAM is initialized and before CAR is disabled.
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*/
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movl $MSR_FAM10, %ecx
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rdmsr
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@ -122,23 +129,13 @@ CAR_FAM10_out:
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wrmsr
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/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
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/* read-address has to be stored in the ecx register */
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movl $MSR_FAM10, %ecx
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/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
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rdmsr
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/* Set bit 35 to 1 in EAX:EDX */
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bts $35-32, %edx
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/* write back the modified register EDX:EAX to the MSR specified in ECX */
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bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
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wrmsr
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/* Erratum 343 end */
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#if CONFIG_MMCONF_SUPPORT
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/* Set MMIO Config space BAR */
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/* Set MMIO Config space BAR. */
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movl $MSR_MCFG_BASE, %ecx
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rdmsr
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@ -152,7 +149,7 @@ CAR_FAM10_out:
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CAR_FAM10_out_post_errata:
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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/* Set MtrrFixDramModEn for clear fixed MTRR. */
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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rdmsr
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@ -160,7 +157,7 @@ enable_fixed_mtrr_dram_modify:
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orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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/* Clear all MTRRs */
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/* Clear all MTRRs. */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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@ -176,7 +173,8 @@ clear_fixed_var_mtrr:
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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/*
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* 0x06 is the WB IO type for a given 4k segment.
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* 0x1e is the MEM IO type for a given 4k segment (K10 and above).
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* segs is the number of 4k segments in the area of the particular
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* register we want to use for CAR.
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@ -184,7 +182,8 @@ clear_fixed_var_mtrr_out:
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*/
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.macro extractmask segs, reg
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.if \segs <= 0
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/* The xorl here is superfluous because at the point of first execution
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/*
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* The xorl here is superfluous because at the point of first execution
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* of this macro, %eax and %edx are cleared. Later invocations of this
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* macro will have a monotonically increasing segs parameter.
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*/
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@ -216,18 +215,20 @@ clear_fixed_var_mtrr_out:
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.endif /* if \segs <= 0 */
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.endm
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/* size is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size
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/*
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* size is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size.
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*/
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.macro simplemask carsize, windowoffset
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.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
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extractmask gas_bug_workaround, %eax
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.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
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extractmask gas_bug_workaround, %edx
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/* Without the gas bug workaround, the entire macro would consist only of the
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* two lines below.
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extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
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extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
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/*
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* Without the gas bug workaround, the entire macro would consist
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* only of the two lines below:
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* extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
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* extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
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*/
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.endm
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@ -242,18 +243,18 @@ clear_fixed_var_mtrr_out:
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#endif
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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/* Enable caching for 32K-64K using fixed MTRR. */
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movl $MTRRfix4K_C0000_MSR, %ecx
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simplemask CacheSize, 0x8000
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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/* Enable caching for 0-32K using fixed MTRR. */
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movl $MTRRfix4K_C8000_MSR, %ecx
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simplemask CacheSize, 0
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wrmsr
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/* enable memory access for first MBs using top_mem */
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/* Enable memory access for first MBs using top_mem. */
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movl $TOP_MEM, %ecx
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xorl %edx, %edx
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movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
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@ -267,8 +268,8 @@ clear_fixed_var_mtrr_out:
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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/* Enable write base caching so we can do execute in place (XIP)
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* on the flash ROM.
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*/
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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@ -285,14 +286,13 @@ wbcache_post_fam10_setup:
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
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/* Set the default memory type and enable fixed and variable MTRRs */
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/* Set the default memory type and enable fixed and variable MTRRs. */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
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wrmsr
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/* Enable the MTRRs and IORRs in SYSCFG */
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/* Enable the MTRRs and IORRs in SYSCFG. */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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@ -300,35 +300,35 @@ wbcache_post_fam10_setup:
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post_code(0xa1)
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/* enable cache */
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/* Enable cache. */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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jmp_if_k8(fam10_end_part1)
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/* So we need to check if it is BSP */
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/* So we need to check if it is BSP. */
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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bt $8, %eax /* BSC */
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jnc CAR_FAM10_ap
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fam10_end_part1:
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post_code(0xa2)
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/* Read the range with lodsl*/
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/* Read the range with lodsl. */
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cld
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movl $CacheBase, %esi
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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/* Clear the range. */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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/* set up the stack pointer */
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/* Set up the stack pointer. */
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movl $(CacheBase + CacheSize - GlobalVarSize), %eax
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movl %eax, %esp
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@ -336,27 +336,32 @@ fam10_end_part1:
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jmp CAR_FAM10_ap_out
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CAR_FAM10_ap:
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/* need to set stack pointer for AP */
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/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
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/* So need to get the NodeID and CoreID at first */
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/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
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/*
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* Need to set stack pointer for AP.
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* It will be from:
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* CacheBase + (CacheSize - GlobalVarSize) / 2
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* - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
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* So need to get the NodeID and CoreID at first.
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* If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
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* to reverse it.
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*/
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/* store our init detected */
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/* Store our init detected. */
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movl %ebx, %esi
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/* get the coreid bits at first */
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/* Get the coreid bits at first. */
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movl $0x80000008, %eax
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cpuid
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shrl $12, %ecx
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andl $0x0f, %ecx
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movl %ecx, %edi
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/* get the initial apic id */
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/* Get the initial APIC ID. */
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movl $1, %eax
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cpuid
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shrl $24, %ebx
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/* get the nb cfg bit 54 */
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/* Get the nb cfg bit 54. */
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movl $0xc001001f, %ecx /* NB_CFG_MSR */
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rdmsr
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movl %edi, %ecx /* CoreID bits */
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@ -365,13 +370,13 @@ CAR_FAM10_ap:
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rolb %cl, %bl
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roll_cfg:
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/* calculate stack pointer */
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/* Calculate stack pointer. */
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movl $CacheSizeAPStack, %eax
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mull %ebx
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movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
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movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
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subl %eax, %esp
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/* retrive init detected */
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/* Retrive init detected. */
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movl %esi, %ebx
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post_code(0xa4)
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@ -380,35 +385,38 @@ CAR_FAM10_ap_out:
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post_code(0xa5)
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/* disable SSE */
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/* Disable SSE. */
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movl %cr4, %eax
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andl $~(3<<9), %eax
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andl $~(3 << 9), %eax
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movl %eax, %cr4
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/* Restore the BIST result */
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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/* We need to set EBP? No need. */
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movl %esp, %ebp
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pushl %ebx /* init detected */
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pushl %eax /* bist */
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pushl %ebx /* Init detected. */
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pushl %eax /* BIST */
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call cache_as_ram_main
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/* We will not go back */
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/* We will not go back. */
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post_code(0xaf) /* Should never see this postcode */
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post_code(0xaf) /* Should never see this POST code. */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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var_iorr_msr:
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.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
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mem_top:
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.long 0xC001001A, 0xC001001D
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.long 0x000 /* NULL, end of table */
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@ -21,18 +21,18 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/lapic_def.h>
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/* Save the BIST result */
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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/* Save the BIST result. */
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movl %eax, %ebp
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CacheAsRam:
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// Check whether the processor has HT capability
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/* Check whether the processor has HT capability. */
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movl $01, %eax
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cpuid
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btl $28, %edx
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@ -41,20 +41,26 @@ CacheAsRam:
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cmpb $01, %bh
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jbe NotHtProcessor
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// It is a HT processor; Send SIPI to the other logical processor
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// within this processor so that the CAR related common system
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// registers are programmed accordingly.
|
||||
/*
|
||||
* It is a HT processor. Send SIPI to the other logical processor
|
||||
* within this processor so that the CAR related common system
|
||||
* registers are programmed accordingly.
|
||||
*/
|
||||
|
||||
// Use some register that is common to both logical processors
|
||||
// as semaphore. Refer Appendix B, Vol.3
|
||||
/*
|
||||
* Use some register that is common to both logical processors
|
||||
* as semaphore. Refer Appendix B, Vol.3.
|
||||
*/
|
||||
xorl %eax, %eax
|
||||
xorl %edx, %edx
|
||||
movl $MTRRfix64K_00000_MSR, %ecx
|
||||
wrmsr
|
||||
|
||||
// Figure out the logical AP's APIC ID; the following logic will
|
||||
// work only for processors with 2 threads.
|
||||
// Refer to Vol 3. Table 7-1 for details about this logic
|
||||
/*
|
||||
* Figure out the logical AP's APIC ID; the following logic will
|
||||
* work only for processors with 2 threads.
|
||||
* Refer to Vol 3. Table 7-1 for details about this logic.
|
||||
*/
|
||||
movl $0xFEE00020, %esi
|
||||
movl (%esi), %ebx
|
||||
andl $0xFF000000, %ebx
|
||||
|
|
@ -66,17 +72,19 @@ CacheAsRam:
|
|||
LogicalAP0:
|
||||
orb $0x01, %bl
|
||||
Send_SIPI:
|
||||
bswapl %ebx // ebx - logical AP's APIC ID
|
||||
bswapl %ebx /* EBX - logical AP's APIC ID. */
|
||||
|
||||
// Fill up the IPI command registers in the Local APIC mapped to
|
||||
// default address and issue SIPI to the other logical processor
|
||||
// within this processor die.
|
||||
/*
|
||||
* Fill up the IPI command registers in the Local APIC mapped to
|
||||
* default address and issue SIPI to the other logical processor
|
||||
* within this processor die.
|
||||
*/
|
||||
Retry_SIPI:
|
||||
movl %ebx, %eax
|
||||
movl $0xFEE00310, %esi
|
||||
movl %eax, (%esi)
|
||||
|
||||
// SIPI vector - F900:0000
|
||||
/* SIPI vector - F900:0000 */
|
||||
movl $0x000006F9, %eax
|
||||
movl $0xFEE00300, %esi
|
||||
movl %eax, (%esi)
|
||||
|
|
@ -91,7 +99,7 @@ SIPI_Delay:
|
|||
andl $0x00001000, %eax
|
||||
jnz Retry_SIPI
|
||||
|
||||
// Wait for the Logical AP to complete initialization
|
||||
/* Wait for the Logical AP to complete initialization. */
|
||||
LogicalAP_SIPINotdone:
|
||||
movl $MTRRfix64K_00000_MSR, %ecx
|
||||
rdmsr
|
||||
|
|
@ -99,14 +107,13 @@ LogicalAP_SIPINotdone:
|
|||
jz LogicalAP_SIPINotdone
|
||||
|
||||
NotHtProcessor:
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
/* Set the default memory type and enable fixed and variable MTRRs. */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
|
||||
wrmsr
|
||||
|
||||
/* Clear all MTRRs */
|
||||
/* Clear all MTRRs. */
|
||||
xorl %edx, %edx
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
|
||||
|
|
@ -126,6 +133,7 @@ fixed_mtrr_msr:
|
|||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
|
|
@ -135,14 +143,16 @@ var_mtrr_msr:
|
|||
|
||||
clear_fixed_var_mtrr_out:
|
||||
|
||||
/* 0x06 is the WB IO type for a given 4k segment.
|
||||
/*
|
||||
* 0x06 is the WB IO type for a given 4k segment.
|
||||
* segs is the number of 4k segments in the area of the particular
|
||||
* register we want to use for CAR.
|
||||
* reg is the register where the IO type should be stored.
|
||||
*/
|
||||
.macro extractmask segs, reg
|
||||
.if \segs <= 0
|
||||
/* The xorl here is superfluous because at the point of first execution
|
||||
/*
|
||||
* The xorl here is superfluous because at the point of first execution
|
||||
* of this macro, %eax and %edx are cleared. Later invocations of this
|
||||
* macro will have a monotonically increasing segs parameter.
|
||||
*/
|
||||
|
|
@ -158,18 +168,20 @@ clear_fixed_var_mtrr_out:
|
|||
.endif
|
||||
.endm
|
||||
|
||||
/* size is the cache size in bytes we want to use for CAR.
|
||||
* windowoffset is the 32k-aligned window into CAR size
|
||||
/*
|
||||
* size is the cache size in bytes we want to use for CAR.
|
||||
* windowoffset is the 32k-aligned window into CAR size.
|
||||
*/
|
||||
.macro simplemask carsize, windowoffset
|
||||
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
|
||||
extractmask gas_bug_workaround, %eax
|
||||
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
|
||||
extractmask gas_bug_workaround, %edx
|
||||
/* Without the gas bug workaround, the entire macro would consist only of the
|
||||
* two lines below.
|
||||
extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
|
||||
extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
|
||||
/*
|
||||
* Without the gas bug workaround, the entire macro would consist
|
||||
* only of the two lines below:
|
||||
* extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
|
||||
* extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
|
||||
*/
|
||||
.endm
|
||||
|
||||
|
|
@ -184,13 +196,13 @@ clear_fixed_var_mtrr_out:
|
|||
#endif
|
||||
|
||||
#if CacheSize > 0x8000
|
||||
/* enable caching for 32K-64K using fixed mtrr */
|
||||
/* Enable caching for 32K-64K using fixed MTRR. */
|
||||
movl $MTRRfix4K_C0000_MSR, %ecx
|
||||
simplemask CacheSize, 0x8000
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* enable caching for 0-32K using fixed mtrr */
|
||||
/* Enable caching for 0-32K using fixed MTRR. */
|
||||
movl $MTRRfix4K_C8000_MSR, %ecx
|
||||
simplemask CacheSize, 0
|
||||
wrmsr
|
||||
|
|
@ -203,8 +215,9 @@ clear_fixed_var_mtrr_out:
|
|||
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
|
||||
#endif
|
||||
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
/*
|
||||
* Enable write base caching so we can do execute in place (XIP)
|
||||
* on the flash ROM.
|
||||
*/
|
||||
movl $MTRRphysBase_MSR(1), %ecx
|
||||
xorl %edx, %edx
|
||||
|
|
@ -218,27 +231,27 @@ clear_fixed_var_mtrr_out:
|
|||
wrmsr
|
||||
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
|
||||
|
||||
/* enable cache */
|
||||
/* Enable cache. */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Read the range with lodsl*/
|
||||
/* Read the range with lodsl. */
|
||||
movl $CacheBase, %esi
|
||||
cld
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
rep lodsl
|
||||
|
||||
/* Clear the range */
|
||||
/* Clear the range. */
|
||||
movl $CacheBase, %edi
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
|
||||
#if 0
|
||||
/* check the cache as ram */
|
||||
/* Check the cache as ram. */
|
||||
movl $CacheBase, %esi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
.xin1:
|
||||
movl %esi, %eax
|
||||
movl %eax, (%esi)
|
||||
|
|
@ -249,7 +262,7 @@ clear_fixed_var_mtrr_out:
|
|||
.xout1:
|
||||
|
||||
movl $CacheBase, %esi
|
||||
// movl $(CacheSize>>2), %ecx
|
||||
// movl $(CacheSize >> 2), %ecx
|
||||
movl $4, %ecx
|
||||
.xin1x:
|
||||
movl %esi, %eax
|
||||
|
|
@ -263,7 +276,7 @@ clear_fixed_var_mtrr_out:
|
|||
|
||||
movl (%esi), %eax
|
||||
cmpb 0xff, %al
|
||||
je .xin2 /* dont show */
|
||||
je .xin2 /* Don't show. */
|
||||
|
||||
movl $0x4000, %edx
|
||||
.testx2:
|
||||
|
|
@ -271,7 +284,8 @@ clear_fixed_var_mtrr_out:
|
|||
decl %edx
|
||||
jnz .testx2
|
||||
|
||||
.xin2: decl %ecx
|
||||
.xin2:
|
||||
decl %ecx
|
||||
je .xout1x
|
||||
add $4, %esi
|
||||
jmp .xin1x
|
||||
|
|
@ -281,21 +295,22 @@ clear_fixed_var_mtrr_out:
|
|||
movl $(CacheBase + CacheSize - 4), %eax
|
||||
movl %eax, %esp
|
||||
lout:
|
||||
/* Restore the BIST result */
|
||||
/* Restore the BIST result. */
|
||||
movl %ebp, %eax
|
||||
|
||||
/* We need to set ebp ? No need */
|
||||
/* We need to set EBP? No need. */
|
||||
movl %esp, %ebp
|
||||
pushl %eax /* bist */
|
||||
pushl %eax /* BIST */
|
||||
call main
|
||||
|
||||
/* We don't need cache as ram for now on */
|
||||
/* disable cache */
|
||||
/* We don't need CAR for now on. */
|
||||
|
||||
/* Disable cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(0x1<<30),%eax
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* clear sth */
|
||||
/* Clear sth. */
|
||||
movl $MTRRfix4K_C8000_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
xorl %eax, %eax
|
||||
|
|
@ -306,25 +321,25 @@ lout:
|
|||
wrmsr
|
||||
#endif
|
||||
|
||||
/* Set the default memory type and disable fixed
|
||||
* and enable variable MTRRs
|
||||
/*
|
||||
* Set the default memory type and disable fixed
|
||||
* and enable variable MTRRs.
|
||||
*/
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Disable Fixed MTRRs */
|
||||
movl $0x00000800, %eax
|
||||
movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
|
||||
wrmsr
|
||||
|
||||
/* enable cache */
|
||||
/* Enable cache. */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* clear boot_complete flag */
|
||||
/* Clear boot_complete flag. */
|
||||
xorl %ebp, %ebp
|
||||
__main:
|
||||
post_code(0x11)
|
||||
cld /* clear direction flag */
|
||||
cld /* Clear direction flag. */
|
||||
|
||||
movl %ebp, %esi
|
||||
|
||||
|
|
|
|||
|
|
@ -25,31 +25,30 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define CacheSize CONFIG_DCACHE_RAM_SIZE
|
||||
#define CacheBase CONFIG_DCACHE_RAM_BASE
|
||||
|
||||
#include <cpu/x86/stack.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
/* Save the BIST result */
|
||||
#define CacheSize CONFIG_DCACHE_RAM_SIZE
|
||||
#define CacheBase CONFIG_DCACHE_RAM_BASE
|
||||
|
||||
/* Save the BIST result. */
|
||||
movl %eax, %ebp
|
||||
|
||||
CacheAsRam:
|
||||
|
||||
/* disable cache */
|
||||
/* Disable cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(0x1<<30),%eax
|
||||
movl %eax,%cr0
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
invd
|
||||
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
/* Set the default memory type and enable fixed and variable MTRRs. */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
|
||||
wrmsr
|
||||
|
||||
/* Clear all MTRRs */
|
||||
/* Clear all MTRRs. */
|
||||
xorl %edx, %edx
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
|
||||
|
|
@ -80,13 +79,13 @@ var_mtrr_msr:
|
|||
clear_fixed_var_mtrr_out:
|
||||
movl $MTRRphysBase_MSR(0), %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
|
||||
movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
|
||||
movl $MTRRphysMask_MSR(0), %ecx
|
||||
/* This assumes we never access addresses above 2^36 in CAR. */
|
||||
movl $0x0000000f,%edx
|
||||
movl $(~(CacheSize-1)|0x800),%eax
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(CacheSize - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
|
||||
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
|
||||
|
|
@ -95,8 +94,9 @@ clear_fixed_var_mtrr_out:
|
|||
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
|
||||
#endif
|
||||
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
/*
|
||||
* Enable write base caching so we can do execute in place (XIP)
|
||||
* on the flash ROM.
|
||||
*/
|
||||
movl $MTRRphysBase_MSR(1), %ecx
|
||||
xorl %edx, %edx
|
||||
|
|
@ -111,39 +111,41 @@ clear_fixed_var_mtrr_out:
|
|||
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000800, %eax
|
||||
movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */
|
||||
wrmsr
|
||||
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Read the range with lodsl*/
|
||||
/* Read the range with lodsl. */
|
||||
cld
|
||||
movl $CacheBase, %esi
|
||||
movl %esi, %edi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
rep lodsl
|
||||
|
||||
movl $CacheBase, %esi
|
||||
movl %esi, %edi
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
|
||||
/* 0x5c5c5c5c is a memory test pattern.
|
||||
* TODO: Check if everything works with the zero pattern as well. */
|
||||
/*xorl %eax, %eax*/
|
||||
xorl $0x5c5c5c5c,%eax
|
||||
/*
|
||||
* 0x5c5c5c5c is a memory test pattern.
|
||||
* TODO: Check if everything works with the zero pattern as well.
|
||||
*/
|
||||
/* xorl %eax, %eax */
|
||||
xorl $0x5c5c5c5c, %eax
|
||||
rep stosl
|
||||
|
||||
#ifdef CARTEST
|
||||
movl REAL_XIP_ROM_BASE, %esi
|
||||
movl %esi, %edi
|
||||
movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
|
||||
movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
|
||||
rep lodsl
|
||||
#endif
|
||||
|
||||
/* The key point of this CAR code is C7 cache does not turn into
|
||||
/*
|
||||
* The key point of this CAR code is C7 cache does not turn into
|
||||
* "no fill" mode, which is not compatible with general CAR code.
|
||||
*/
|
||||
|
||||
|
|
@ -155,7 +157,7 @@ testok:
|
|||
post_code(0x40)
|
||||
xorl %edx, %edx
|
||||
xorl %eax, %eax
|
||||
movl $0x5c5c,%edx
|
||||
movl $0x5c5c, %edx
|
||||
pushl %edx
|
||||
pushl %edx
|
||||
pushl %edx
|
||||
|
|
@ -166,16 +168,16 @@ testok:
|
|||
popl %eax
|
||||
popl %eax
|
||||
popl %eax
|
||||
cmpl %edx,%eax
|
||||
cmpl %edx, %eax
|
||||
jne stackerr
|
||||
#endif
|
||||
|
||||
/* Restore the BIST result */
|
||||
/* Restore the BIST result. */
|
||||
movl %ebp, %eax
|
||||
|
||||
/* We need to set ebp ? No need */
|
||||
/* We need to set EBP? No need. */
|
||||
movl %esp, %ebp
|
||||
pushl %eax /* bist */
|
||||
pushl %eax /* BIST */
|
||||
call main
|
||||
|
||||
/*
|
||||
|
|
@ -184,37 +186,39 @@ testok:
|
|||
* want to go back.
|
||||
*/
|
||||
|
||||
/* We don't need cache as ram for now on */
|
||||
/* disable cache */
|
||||
/* We don't need CAR for now on. */
|
||||
|
||||
/* Disable cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(0x1<<30),%eax
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
|
||||
/* Set the default memory type and disable fixed and enable variable MTRRs */
|
||||
/*
|
||||
* Set the default memory type and disable fixed and enable
|
||||
* variable MTRRs.
|
||||
*/
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
|
||||
/* Enable Variable and Disable Fixed MTRRs */
|
||||
movl $0x00000800, %eax
|
||||
movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */
|
||||
wrmsr
|
||||
|
||||
/* enable caching for first 1M using variable mtrr */
|
||||
/* Enable caching for first 1M using variable MTRR. */
|
||||
movl $MTRRphysBase_MSR(0), %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(0 | 6), %eax
|
||||
//movl $(0 | MTRR_TYPE_WRBACK), %eax
|
||||
// movl $(0 | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
|
||||
/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
|
||||
/*
|
||||
* Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
|
||||
* If 1M cacheable, then when S3 resume, there is stange color on
|
||||
* screen for 2 sec. suppose problem of a0000-dfffff and cache.
|
||||
* screen for 2 sec. Suppose problem of a0000-dfffff and cache.
|
||||
* And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
|
||||
*/
|
||||
|
||||
movl $MTRRphysMask_MSR(0), %ecx
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
|
||||
movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
|
||||
movl $((~((0 + 0x80000) - 1)) | 0x800), %eax
|
||||
wrmsr
|
||||
|
||||
movl $MTRRphysBase_MSR(1), %ecx
|
||||
|
|
@ -224,8 +228,8 @@ testok:
|
|||
wrmsr
|
||||
|
||||
movl $MTRRphysMask_MSR(1), %ecx
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
|
||||
movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
|
||||
movl $((~((0 + 0x20000) - 1)) | 0x800), %eax
|
||||
wrmsr
|
||||
|
||||
movl $MTRRphysBase_MSR(2), %ecx
|
||||
|
|
@ -235,11 +239,11 @@ testok:
|
|||
wrmsr
|
||||
|
||||
movl $MTRRphysMask_MSR(2), %ecx
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
|
||||
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
|
||||
movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
|
||||
wrmsr
|
||||
|
||||
/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
|
||||
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
|
||||
movl $MTRRphysBase_MSR(3), %ecx
|
||||
xorl %edx, %edx
|
||||
movl $REAL_XIP_ROM_BASE,%eax
|
||||
|
|
@ -248,23 +252,23 @@ testok:
|
|||
|
||||
movl $MTRRphysMask_MSR(3), %ecx
|
||||
xorl %edx, %edx
|
||||
movl $CONFIG_XIP_ROM_SIZE,%eax
|
||||
movl $CONFIG_XIP_ROM_SIZE, %eax
|
||||
decl %eax
|
||||
notl %eax
|
||||
orl $(0 | 0x800), %eax
|
||||
wrmsr
|
||||
|
||||
/* enable cache */
|
||||
/* Enable cache. */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
invd
|
||||
|
||||
/* clear boot_complete flag */
|
||||
/* Clear boot_complete flag. */
|
||||
xorl %ebp, %ebp
|
||||
__main:
|
||||
post_code(0x11)
|
||||
cld /* clear direction flag */
|
||||
cld /* Clear direction flag. */
|
||||
|
||||
movl %ebp, %esi
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue