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None of the cs5536 settings in devicetree.cb were ever used and nobody noticed. 

Fix it!

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-22 10:44:08 +00:00 committed by Stefan Reinauer
parent ba09695b58
commit 4292685f5a
2 changed files with 29 additions and 2 deletions
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7
src/include/cpu/amd/gx2def.h
View File

@ -693,4 +693,11 @@
#define PMLogic_BASE ( 0x9D00)
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if defined(__PRE_RAM__)
#else
void cpubug(void);
#endif
#endif
#endif /* CPU_AMD_GX2DEF_H */

24
src/southbridge/amd/cs5536/cs5536.c
View File

@ -527,10 +527,24 @@ void chipsetinit(void)
device_t dev;
msr_t msr;
u32 msrnum;
struct southbridge_amd_cs5536_config *sb =
(struct southbridge_amd_cs5536_config *)dev->chip_info;
struct southbridge_amd_cs5536_config *sb;
struct msrinit *csi;
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
if (!dev) {
printk(BIOS_ERR, "CS5536 not found.\n");
return;
}
sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
if (!sb) {
printk(BIOS_ERR, "CS5536 configuration not found.\n");
return;
}
post_code(P80_CHIPSET_INIT);
/* we hope NEVER to be in coreboot when S3 resumes
@ -599,6 +613,12 @@ static void southbridge_init(struct device *dev)
*/
printk(BIOS_ERR, "cs5536: %s\n", __func__);
if (!sb) {
printk(BIOS_ERR, "CS5536 configuration not found.\n");
return;
}
setup_i8259();
lpc_init(sb);
uarts_init(sb);