nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
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5 changed files with 21 additions and 35 deletions
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@ -80,4 +80,13 @@ config MAX_CPUS
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int
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default 4
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config FIXED_MCHBAR_MMIO_BASE
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default 0xfed14000
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config FIXED_DMIBAR_MMIO_BASE
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default 0xfed18000
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config FIXED_EPBAR_MMIO_BASE
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default 0xfed19000
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endif
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@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "hostbridge.asl"
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#include "../i945.h"
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/* Operating System Capabilities Method */
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Method (_OSC, 4)
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@ -38,9 +37,9 @@ Device (PDRC)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
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Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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@ -143,9 +143,9 @@ static void i945_setup_bars(void)
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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/* Set up all hardcoded northbridge BARs */
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pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
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pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
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pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
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pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
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pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
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pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
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/* vram size from CMOS option */
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@ -715,7 +715,7 @@ static void i945_setup_root_complex_topology(void)
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EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
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EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
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EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
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EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
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@ -734,11 +734,11 @@ static void i945_setup_root_complex_topology(void)
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DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
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DMIBAR32(DMILE2A) = DEFAULT_EPBAR;
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DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE;
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/* PCI Express x16 Port Root Topology */
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if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) {
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pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR);
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pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE);
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pci_or_config32(p2peg, LE1D, 1 << 0);
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}
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}
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@ -751,7 +751,7 @@ static void ich7_setup_root_complex_topology(void)
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RCBA32(ULD) |= (1 << 24) | (1 << 16);
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RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
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RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
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/* Write ESD.CID to TCID */
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RCBA32(RP1D) |= (2 << 16);
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RCBA32(RP2D) |= (2 << 16);
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@ -3,7 +3,7 @@
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#ifndef NORTHBRIDGE_INTEL_I945_H
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#define NORTHBRIDGE_INTEL_I945_H
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#include "memmap.h"
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#define DEFAULT_X60BAR 0xfed13000
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#include <southbridge/intel/i82801gx/i82801gx.h>
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@ -90,9 +90,7 @@
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* MCHBAR
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*/
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#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#include <northbridge/intel/common/fixed_bars.h>
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/* Chipset Control Registers */
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#define FSBPMC3 0x40 /* 32bit */
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@ -274,10 +272,6 @@
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
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#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
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#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
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#define EPPVCCAP1 0x004 /* 32bit */
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#define EPPVCCAP2 0x008 /* 32bit */
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@ -305,10 +299,6 @@
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* DMIBAR
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*/
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#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
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#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
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#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
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#define DMIVCECH 0x000 /* 32bit */
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#define DMIPVCCAP1 0x004 /* 32bit */
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#define DMIPVCCAP2 0x008 /* 32bit */
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@ -1,12 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef NORTHBRIDGE_INTEL_I945_MEMMAP_H
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#define NORTHBRIDGE_INTEL_I945_MEMMAP_H
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/* Northbridge BARs */
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#define DEFAULT_X60BAR 0xfed13000
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#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
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#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#endif
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