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nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors

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Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-01-20 12:32:22 +01:00 committed by Patrick Georgi
parent e88f705946
commit 4299cb4829
5 changed files with 21 additions and 35 deletions
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9
src/northbridge/intel/i945/Kconfig
View file

@ -80,4 +80,13 @@ config MAX_CPUS
int int
default 4 default 4
config FIXED_MCHBAR_MMIO_BASE
default 0xfed14000
config FIXED_DMIBAR_MMIO_BASE
default 0xfed18000
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
endif endif

7
src/northbridge/intel/i945/acpi/i945.asl
View file

@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../i945.h"
/* Operating System Capabilities Method */ /* Operating System Capabilities Method */
Method (_OSC, 4) Method (_OSC, 4)
@ -38,9 +37,9 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH

14
src/northbridge/intel/i945/early_init.c
View file

@ -143,9 +143,9 @@ static void i945_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static northbridge registers..."); printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */ /* Set up all hardcoded northbridge BARs */
pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */ /* vram size from CMOS option */
@ -715,7 +715,7 @@ static void i945_setup_root_complex_topology(void)
EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
@ -734,11 +734,11 @@ static void i945_setup_root_complex_topology(void)
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
DMIBAR32(DMILE2A) = DEFAULT_EPBAR; DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE;
/* PCI Express x16 Port Root Topology */ /* PCI Express x16 Port Root Topology */
if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) {
pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE);
pci_or_config32(p2peg, LE1D, 1 << 0); pci_or_config32(p2peg, LE1D, 1 << 0);
} }
} }
@ -751,7 +751,7 @@ static void ich7_setup_root_complex_topology(void)
RCBA32(ULD) |= (1 << 24) | (1 << 16); RCBA32(ULD) |= (1 << 24) | (1 << 16);
RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
/* Write ESD.CID to TCID */ /* Write ESD.CID to TCID */
RCBA32(RP1D) |= (2 << 16); RCBA32(RP1D) |= (2 << 16);
RCBA32(RP2D) |= (2 << 16); RCBA32(RP2D) |= (2 << 16);

14
src/northbridge/intel/i945/i945.h
View file

@ -3,7 +3,7 @@
#ifndef NORTHBRIDGE_INTEL_I945_H #ifndef NORTHBRIDGE_INTEL_I945_H
#define NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H
#include "memmap.h" #define DEFAULT_X60BAR 0xfed13000
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
@ -90,9 +90,7 @@
* MCHBAR * MCHBAR
*/ */
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #include <northbridge/intel/common/fixed_bars.h>
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
/* Chipset Control Registers */ /* Chipset Control Registers */
#define FSBPMC3 0x40 /* 32bit */ #define FSBPMC3 0x40 /* 32bit */
@ -274,10 +272,6 @@
* EPBAR - Egress Port Root Complex Register Block * EPBAR - Egress Port Root Complex Register Block
*/ */
#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
#define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */
@ -305,10 +299,6 @@
* DMIBAR * DMIBAR
*/ */
#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
#define DMIVCECH 0x000 /* 32bit */ #define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */ #define DMIPVCCAP2 0x008 /* 32bit */

12
src/northbridge/intel/i945/memmap.h
View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef NORTHBRIDGE_INTEL_I945_MEMMAP_H
#define NORTHBRIDGE_INTEL_I945_MEMMAP_H
/* Northbridge BARs */
#define DEFAULT_X60BAR 0xfed13000
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#endif